17-10-2016, 03:41 PM
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ABSTRACT
In the last 10 years, FPGA circuits have developed rapidly, because of their flexibility, their ease of use and the low cost to design a function with them. However, the internal memories used in FPGA circuit could limit their future use. Most FPGA circuits use SRAM based flip-flop as internal memory. But since SRAM is volatile, both the configuration and information stored is lost. Internal Flash technology is sometime used to replace the external memory. However, it’s slow re-programming and its limited number of writing cycles (up to 106) prevents its use to replace SRAM. By working at high writing and reading speed, MRAM (Magnetic RAM) technology is one of the best solutions to bring complete non-volatility to the FPGA technology while keeping the power dissipation low. An MRAM can be re-programmed 1012 times and has a large retention time up to 10 years. The objective of our project is to contribute one such storage device by making Non-Volatile SRAM based on Magnetic Tunnel Junction (MTJ). The circuit has been implemented using Tanner Tools using 0.25μm technology and the output waveforms are obtained.
1. Introduction
Most of the field-programmable gate arrays (FPGAs) are currently SRAM based [1]. In these devices, configuration memory is distributed throughout the chip. Each memory point has to be readable independently because each of these points is used to drive a transistor’s gate or a Lookup table (LUT) input [1]. Nevertheless, for writing operation, the configuration memory is organized as a classical memory array. Speed limitation of the configuration is linked to the size of the words that the memory can write at a time. Multiplying the number of memory arrays can reduce this time and allows parallel loading of the configuration bit stream with partial dynamic reconfiguration capabilities. The small access time of the SRAM makes it popular in the FPGA industry. Nonetheless, its volatility and the need of an external nonvolatile memory to store the configuration data make it not suitable for nowadays embedded applications. Indeed, in embedded FPGA devices, the use of a nonvolatile internal memory like flash technology allows the chip to be powered down in the standby mode when not in use in order to reduce power consumption. Some FPGAs and CPLDs use flash memory like Actel’s fusion products. Indeed, these FPGAs use flash memory in their configuration layer which makes it ready to run at power up. However, distribution of the memory all over the chip raises some technological constraints and needs additional masks (10 to 15 for the flash technology) and dedicated process steps thereby increasing the chip cost. Moreover, these FPGAs are not sufficiently flexible because they do neither provide partial or dynamical reconfiguration nor fast reprogramming speed due to the high-access time inherent to the flash memory.
The use of nonvolatile memories such as MRAMs helps to overcome the drawbacks of classical SRAM-based FPGAs without significant speed penalty. Besides its advantage that lies in power saving during the standby mode, it also benefits to the configuration time reduction since there is no need to load the configuration data from an external nonvolatile memory as is usual in SRAM-based FPGAs. Furthermore, during the FPGA circuit operation, the magnetic tunneling junctions can be written which allows a dynamic (or shadowed) configuration and further increases the flexibility of FPGA circuits based on the MRAM.
STATIC RANDOM ACCESS MEMORY
Static Random Access Memory is a type of semi-conductor memory where the word static indicates that, unlike DRAM it does not need to be periodically refreshed, as SRAM uses bi-stable latching circuitry to store each bit. SRAM inhibits data remanence but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit.
Access to the cell is enabled by the word line which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margin. During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs.
In a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards.
The symmetric structure of SRAMs also allows for differential signalling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down. SRAM is used in personal computers, workstations, routers and peripheral equipment.
SENSING CIRCUIT IN SRAM
A sense amplifier is an amplifier that senses the output on the bit lines and amplifies it. The sense amplifier that is used in the design is the ‘Differential Voltage Sense Amplifier’. It takes small signal differential inputs (i.e. the bit line voltages), and amplifies them to a large-signal single-ended output. The differential approach presents numerous advantages over its single-ended counterpart. One of the advantages is the common mode rejection. It means that such an amplifier rejects noise that is equally injected in both the inputs.
The impact of those noise signals can be substantial, especially since the amplitude of the signal to be sensed is generally small. The effectiveness of a differential amplifier is characterized by its ability to reject the common noise and amplify the true difference between the signals. The signals common to both inputs are suppressed at the output of the amplifier by a ratio called the common-mode-rejection-ratio (CMRR) .
MTJ uses differentiate between the two logic states. It contains two Ferro-magnetic layers which are separated from each other by a thin layer of insulator also known as barrier. The Ferro-magnetic layers are made up of Cobalt-Ferrous-Boron (CoFeBo). In Fig 3.2, Insulator layer or the barrier is made up of Magnesium-Oxide (MgO) is show.
TUNNEL MAGNETO RESISTANCE (TMR)
The ratio between the two resistances at zero bias is called as TMR ratio. Higher the TMR ratio, lower the resistance area.
TMR = RAP −RP × 100% (1)
RP
Where, RAP is the electrical resistance in the anti-parallel state and RP is the electrical resistance in the parallel state.
The fixed layer in MTJ is a permanent magnet whereas the free layer has Ferro-magnetic material that can be magnetised by passing a current (I) through it. Based on the field formed in the free layer the fields forms between the two layers. If both fields are in anti-parallel direction then high resistance is formed between the two layers .
THEORETICAL ANALYSIS OF MTJ
BARRIER CONDUCTANCE
Electron tunnelling through a thin insulating layer between two normal metal electrodes has been studied theoretically and experimentally for almost 40 years. Calculations based on rectangular and trapezoidal potential barriers using various approximations have shown that the tunnelling current should be directly proportional to the applied voltage for voltages very much lesser than the barrier height and should increase exponentially with voltage when the voltage becomes comparable to the barrier height [11].
We take a trapezoidal barrier shape and consider the two extreme cases of
The WKB approximation.
Perfectly sharp boundaries between metal and insulator.
CALCULATION OF BARRIER CONDUCTANCE
Consider two metals a and b separated by an arbitrary potential barrier ф(x) [10]. Assuming the WKB approximation inside the barrier the tunnelling current density is given by
j = 4 π e Σ ∞ dE E E − eV P E × [f E − f E − eV ] (1)
ρb
h −∞ xρa x
where, Eρa and Eρb are the densities of states for a given transverse momentum and total energy E for system a and b respectively. The f (E) is the usual Fermi distribution function. Ex is the total energy in the direction perpendicular to the barrier. P (Ex) is the tunnelling probability which has the form.
P E = A exp (− 2 d{2m φ x`, V − E }1 2dx`) (2)
x h 0 x
where, d is the barrier thickness and φ x, V is the barrier height at the voltage V and the position x in the barrier. The pre-exponential factor A may depend on Ex.
APPROXIMATION USED BY SIMMONS
The approximation used by the Simmons is to replace the barrier φ x,V by an average barrier φ V hence it is constant throughout the barrier and the tunnelling probability is simply reduced to
P E = A exp {(−( 8m ) 1 2β φ V − E 1 2 0 dxI } (3)
x
x h 2 d
The correction factor β is assumed independent of Ex in order to perform the integration. By applying this approximation all the information about barrier asymmetry is lost [12].
The tunnelling behaviour is usually modelled using the Simmons theory for tunnel junctions. The general equation for this theory is given below.
Where A is the area of the cross section.
Now, the conductance physics model using the above equations, formed by Brinkman in 1970 is given below. It features the voltage bias dependence and is deeply influenced by the height of the barrier [13].
Here, ∅ = 0 since barrier is symmetric.
The simplified resistance equations of the above equations (8) and (9) are given below which are used to express the resistance performance of an MTJ.
4×h ×∅
R(0) is the higher value of resistance which is obtained due to the anti-parallel fields formed between the two ferromagnetic layers given by equation (12).
Whereas R(V) is the lower resistance value which is formed due to the tunnelling effect that occurs between the ferromagnetic layers through the insulating layer due to the parallel fields that are formed between the two ferromagnetic layers given by equation
Another advantage of Spin-MTJ technology is that the storage element does not take much die area, because it is processed over the chip surface (see Fig.4). By using STMicroelectronics 90nm CMOS technology and a behavior Spin-MTJ simulation Model [5], Spin-LUT and Spin-FF have been demonstrated that they could work with high speed performance and small layout surface (Fig.5). The “high” MTJ resistance is actually more adapted to nanoelectronics. The 1995 publications started a race to develop the magnetic random access memory, or MRAM [13]. Figure 5A displays the principle of this magnetic solid state memory, in the basic “cross point” architecture. The binary information “0” and “1” is recorded on the two opposite orientations of the magnetization of the free layer along its easy magnetization axis. The MTJs are connected to the crossing points of two perpendicular arrays of parallel conducting lines. For writing, current pulses are sent through one line of each array, and only at the crossing point of these lines the resulting magnetic field is high enough to orient the magnetization of the free layer. For reading, one measures the resistance between the two lines connecting the addressed cell. In principle, this cross point architecture promises very high densities. In practice, the amplitude of magnetoresistance remains too low for fast, reliable reading because of the unwanted current paths besides the direct one through the addressed cell. So realistic cells add one transistor per cell, resulting in more complex 1T/1MTJ cell architectures such as the one represented in Figure 5B. Several demonstrator circuits were rapidly presented by most leading semiconductor companies, culminating with the first MRAM product, a 4 Mbit standalone memory [33] commercialized by Freescale in 2006, and soon voted “Product of the Year” by "Electronics Products Magazine" (Jan. 2007) (Figure 5C).
The MRAM potentially combines key advantages such as non volatility, infinite endurance, and fast random access (down to 5ns read/write demonstrated, cf [34]), that make it a likely candidate for becoming the “universal memory”, one of the “Holy Grails” of Nano electronics. Such a memory is able to provide data/code (Flash, ROM) and execution (DRAM, SRAM) storage using a single memory technology on the same die. Moreover, Freescale introduced in June 2007 a new version able to work in the enhanced -40°C to 105°C temperature range, i.e. qualifying for military and space applications where the MRAM will also benefit from the intrinsic radiation hardness of magnetic storage.
CONCLUSION
Most FPGA circuits use SRAM based flip-flop as internal memory. But since SRAM is volatile, both the configuration and information stored is lost. Hence a Non-volatile SRAM is designed using a Magnetic Tunnel Junction and is simulated in the Tanner Tools. The two resistances are calculated and are found to be1.2kΩ for logic ‘0’ and 260Ω for logic ‘1’. The currents flowing through the MTJ during the two states are easily differentiable. At logic ‘0’, 120μA current flows whereas at logic ‘1’,0.3mA current flows. Thus the maximum current flow is as low as 360μA which is very low.The TMR ratio of 314.45% is obtained. The more the TMR ratio, the more will be the resistance area in the MTJ,hence it is easy to differentiate between the two logic states at the output of MTJ. The power consumption of the Non-Volatile SRAM differentiate between the two logic states at the output of MTJ. The power consumption of the Non-Volatile SRAM is found to be 50μW for higher resistance and 110μW for the lower resistance. Hence the SRAM cell which has been designed and realized using MTJ is a non-volatile device and can be used to store the data from the output of the SRAM cell as tabulated in Table I
The application of full adder has been done and the two outputs (SUM and CARRY) are stored in two MTJs. The drain current flowing through it is found and the two resistances are obtained as shown in Table I.
The drain current flowing through the MTJ is obtained as 100μA for logic ‘0’ and 270μA for logic ‘1’ and the voltage obtained across the MTJ is 95mV for logic ‘1’ and 550mV for logic ‘0’. The two resistances obtained are RH(0) for logic ‘0’ and RL(1) for logic ‘1’. Where RH(0) is 5.5kΩ and RL(1) is 330Ω. The input voltage supplied to the MTJ is 0.8 volts.
ABSTRACT
In the last 10 years, FPGA circuits have developed rapidly, because of their flexibility, their ease of use and the low cost to design a function with them. However, the internal memories used in FPGA circuit could limit their future use. Most FPGA circuits use SRAM based flip-flop as internal memory. But since SRAM is volatile, both the configuration and information stored is lost. Internal Flash technology is sometime used to replace the external memory. However, it’s slow re-programming and its limited number of writing cycles (up to 106) prevents its use to replace SRAM. By working at high writing and reading speed, MRAM (Magnetic RAM) technology is one of the best solutions to bring complete non-volatility to the FPGA technology while keeping the power dissipation low. An MRAM can be re-programmed 1012 times and has a large retention time up to 10 years. The objective of our project is to contribute one such storage device by making Non-Volatile SRAM based on Magnetic Tunnel Junction (MTJ). The circuit has been implemented using Tanner Tools using 0.25μm technology and the output waveforms are obtained.
1. Introduction
Most of the field-programmable gate arrays (FPGAs) are currently SRAM based [1]. In these devices, configuration memory is distributed throughout the chip. Each memory point has to be readable independently because each of these points is used to drive a transistor’s gate or a Lookup table (LUT) input [1]. Nevertheless, for writing operation, the configuration memory is organized as a classical memory array. Speed limitation of the configuration is linked to the size of the words that the memory can write at a time. Multiplying the number of memory arrays can reduce this time and allows parallel loading of the configuration bit stream with partial dynamic reconfiguration capabilities. The small access time of the SRAM makes it popular in the FPGA industry. Nonetheless, its volatility and the need of an external nonvolatile memory to store the configuration data make it not suitable for nowadays embedded applications. Indeed, in embedded FPGA devices, the use of a nonvolatile internal memory like flash technology allows the chip to be powered down in the standby mode when not in use in order to reduce power consumption. Some FPGAs and CPLDs use flash memory like Actel’s fusion products. Indeed, these FPGAs use flash memory in their configuration layer which makes it ready to run at power up. However, distribution of the memory all over the chip raises some technological constraints and needs additional masks (10 to 15 for the flash technology) and dedicated process steps thereby increasing the chip cost. Moreover, these FPGAs are not sufficiently flexible because they do neither provide partial or dynamical reconfiguration nor fast reprogramming speed due to the high-access time inherent to the flash memory.
The use of nonvolatile memories such as MRAMs helps to overcome the drawbacks of classical SRAM-based FPGAs without significant speed penalty. Besides its advantage that lies in power saving during the standby mode, it also benefits to the configuration time reduction since there is no need to load the configuration data from an external nonvolatile memory as is usual in SRAM-based FPGAs. Furthermore, during the FPGA circuit operation, the magnetic tunneling junctions can be written which allows a dynamic (or shadowed) configuration and further increases the flexibility of FPGA circuits based on the MRAM.
STATIC RANDOM ACCESS MEMORY
Static Random Access Memory is a type of semi-conductor memory where the word static indicates that, unlike DRAM it does not need to be periodically refreshed, as SRAM uses bi-stable latching circuitry to store each bit. SRAM inhibits data remanence but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit.
Access to the cell is enabled by the word line which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margin. During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs.
In a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards.
The symmetric structure of SRAMs also allows for differential signalling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down. SRAM is used in personal computers, workstations, routers and peripheral equipment.
SENSING CIRCUIT IN SRAM
A sense amplifier is an amplifier that senses the output on the bit lines and amplifies it. The sense amplifier that is used in the design is the ‘Differential Voltage Sense Amplifier’. It takes small signal differential inputs (i.e. the bit line voltages), and amplifies them to a large-signal single-ended output. The differential approach presents numerous advantages over its single-ended counterpart. One of the advantages is the common mode rejection. It means that such an amplifier rejects noise that is equally injected in both the inputs.
The impact of those noise signals can be substantial, especially since the amplitude of the signal to be sensed is generally small. The effectiveness of a differential amplifier is characterized by its ability to reject the common noise and amplify the true difference between the signals. The signals common to both inputs are suppressed at the output of the amplifier by a ratio called the common-mode-rejection-ratio (CMRR) .
MTJ uses differentiate between the two logic states. It contains two Ferro-magnetic layers which are separated from each other by a thin layer of insulator also known as barrier. The Ferro-magnetic layers are made up of Cobalt-Ferrous-Boron (CoFeBo). In Fig 3.2, Insulator layer or the barrier is made up of Magnesium-Oxide (MgO) is show.
TUNNEL MAGNETO RESISTANCE (TMR)
The ratio between the two resistances at zero bias is called as TMR ratio. Higher the TMR ratio, lower the resistance area.
TMR = RAP −RP × 100% (1)
RP
Where, RAP is the electrical resistance in the anti-parallel state and RP is the electrical resistance in the parallel state.
The fixed layer in MTJ is a permanent magnet whereas the free layer has Ferro-magnetic material that can be magnetised by passing a current (I) through it. Based on the field formed in the free layer the fields forms between the two layers. If both fields are in anti-parallel direction then high resistance is formed between the two layers .
THEORETICAL ANALYSIS OF MTJ
BARRIER CONDUCTANCE
Electron tunnelling through a thin insulating layer between two normal metal electrodes has been studied theoretically and experimentally for almost 40 years. Calculations based on rectangular and trapezoidal potential barriers using various approximations have shown that the tunnelling current should be directly proportional to the applied voltage for voltages very much lesser than the barrier height and should increase exponentially with voltage when the voltage becomes comparable to the barrier height [11].
We take a trapezoidal barrier shape and consider the two extreme cases of
The WKB approximation.
Perfectly sharp boundaries between metal and insulator.
CALCULATION OF BARRIER CONDUCTANCE
Consider two metals a and b separated by an arbitrary potential barrier ф(x) [10]. Assuming the WKB approximation inside the barrier the tunnelling current density is given by
j = 4 π e Σ ∞ dE E E − eV P E × [f E − f E − eV ] (1)
ρb
h −∞ xρa x
where, Eρa and Eρb are the densities of states for a given transverse momentum and total energy E for system a and b respectively. The f (E) is the usual Fermi distribution function. Ex is the total energy in the direction perpendicular to the barrier. P (Ex) is the tunnelling probability which has the form.
P E = A exp (− 2 d{2m φ x`, V − E }1 2dx`) (2)
x h 0 x
where, d is the barrier thickness and φ x, V is the barrier height at the voltage V and the position x in the barrier. The pre-exponential factor A may depend on Ex.
APPROXIMATION USED BY SIMMONS
The approximation used by the Simmons is to replace the barrier φ x,V by an average barrier φ V hence it is constant throughout the barrier and the tunnelling probability is simply reduced to
P E = A exp {(−( 8m ) 1 2β φ V − E 1 2 0 dxI } (3)
x
x h 2 d
The correction factor β is assumed independent of Ex in order to perform the integration. By applying this approximation all the information about barrier asymmetry is lost [12].
The tunnelling behaviour is usually modelled using the Simmons theory for tunnel junctions. The general equation for this theory is given below.
Where A is the area of the cross section.
Now, the conductance physics model using the above equations, formed by Brinkman in 1970 is given below. It features the voltage bias dependence and is deeply influenced by the height of the barrier [13].
Here, ∅ = 0 since barrier is symmetric.
The simplified resistance equations of the above equations (8) and (9) are given below which are used to express the resistance performance of an MTJ.
4×h ×∅
R(0) is the higher value of resistance which is obtained due to the anti-parallel fields formed between the two ferromagnetic layers given by equation (12).
Whereas R(V) is the lower resistance value which is formed due to the tunnelling effect that occurs between the ferromagnetic layers through the insulating layer due to the parallel fields that are formed between the two ferromagnetic layers given by equation
Another advantage of Spin-MTJ technology is that the storage element does not take much die area, because it is processed over the chip surface (see Fig.4). By using STMicroelectronics 90nm CMOS technology and a behavior Spin-MTJ simulation Model [5], Spin-LUT and Spin-FF have been demonstrated that they could work with high speed performance and small layout surface (Fig.5). The “high” MTJ resistance is actually more adapted to nanoelectronics. The 1995 publications started a race to develop the magnetic random access memory, or MRAM [13]. Figure 5A displays the principle of this magnetic solid state memory, in the basic “cross point” architecture. The binary information “0” and “1” is recorded on the two opposite orientations of the magnetization of the free layer along its easy magnetization axis. The MTJs are connected to the crossing points of two perpendicular arrays of parallel conducting lines. For writing, current pulses are sent through one line of each array, and only at the crossing point of these lines the resulting magnetic field is high enough to orient the magnetization of the free layer. For reading, one measures the resistance between the two lines connecting the addressed cell. In principle, this cross point architecture promises very high densities. In practice, the amplitude of magnetoresistance remains too low for fast, reliable reading because of the unwanted current paths besides the direct one through the addressed cell. So realistic cells add one transistor per cell, resulting in more complex 1T/1MTJ cell architectures such as the one represented in Figure 5B. Several demonstrator circuits were rapidly presented by most leading semiconductor companies, culminating with the first MRAM product, a 4 Mbit standalone memory [33] commercialized by Freescale in 2006, and soon voted “Product of the Year” by "Electronics Products Magazine" (Jan. 2007) (Figure 5C).
The MRAM potentially combines key advantages such as non volatility, infinite endurance, and fast random access (down to 5ns read/write demonstrated, cf [34]), that make it a likely candidate for becoming the “universal memory”, one of the “Holy Grails” of Nano electronics. Such a memory is able to provide data/code (Flash, ROM) and execution (DRAM, SRAM) storage using a single memory technology on the same die. Moreover, Freescale introduced in June 2007 a new version able to work in the enhanced -40°C to 105°C temperature range, i.e. qualifying for military and space applications where the MRAM will also benefit from the intrinsic radiation hardness of magnetic storage.
CONCLUSION
Most FPGA circuits use SRAM based flip-flop as internal memory. But since SRAM is volatile, both the configuration and information stored is lost. Hence a Non-volatile SRAM is designed using a Magnetic Tunnel Junction and is simulated in the Tanner Tools. The two resistances are calculated and are found to be1.2kΩ for logic ‘0’ and 260Ω for logic ‘1’. The currents flowing through the MTJ during the two states are easily differentiable. At logic ‘0’, 120μA current flows whereas at logic ‘1’,0.3mA current flows. Thus the maximum current flow is as low as 360μA which is very low.The TMR ratio of 314.45% is obtained. The more the TMR ratio, the more will be the resistance area in the MTJ,hence it is easy to differentiate between the two logic states at the output of MTJ. The power consumption of the Non-Volatile SRAM differentiate between the two logic states at the output of MTJ. The power consumption of the Non-Volatile SRAM is found to be 50μW for higher resistance and 110μW for the lower resistance. Hence the SRAM cell which has been designed and realized using MTJ is a non-volatile device and can be used to store the data from the output of the SRAM cell as tabulated in Table I
The application of full adder has been done and the two outputs (SUM and CARRY) are stored in two MTJs. The drain current flowing through it is found and the two resistances are obtained as shown in Table I.
The drain current flowing through the MTJ is obtained as 100μA for logic ‘0’ and 270μA for logic ‘1’ and the voltage obtained across the MTJ is 95mV for logic ‘1’ and 550mV for logic ‘0’. The two resistances obtained are RH(0) for logic ‘0’ and RL(1) for logic ‘1’. Where RH(0) is 5.5kΩ and RL(1) is 330Ω. The input voltage supplied to the MTJ is 0.8 volts.