05-11-2016, 10:14 AM
[attachment=74602]
Overview
This project demonstrates the following audio processing capabilities of the Atlys:
• Recording audio data from the LINE IN and MIC jacks to memory
• Playing back recorded audio data over the LINE OUT and HP jacks
• Generating a square wave that is played on the left, right and then both stereo channels of the LINE OUT and HP jacks.
The project was designed using Xilinx EDK 13.2. It incorporates a custom AC’97 pcore that provides a software accessible interface with the codec hardware. This pcore is included with our BSB support packages so that it may easily be integrated into other EDK designs.
Running the Demo Application
The following equipment is required:
• Digilent Atlys Development Board
• Computer running Xilinx EDK 13.2 or newer
• 1 USB micro cable for programming
• One audio source with 3.5mm TRS wire
• One audio playback device with 3.5mm TRS wire
The following steps outline how to build the project in XPS and then execute the demo application on an Atlys. A basic understanding of Xilinx EDK is assumed. All file paths are given from the folder containing this document:
1) Open up project\system.xmp in XPS. Allow the tools to perform any necessary updates.
2) Export the Hardware design to SDK. This will take some time to complete.
3) Open up a new workspace in Xilinx SDK. If not done automatically, import the generated hardware profile.
4) Create an empty Xilinx C project and a standalone BSP. Copy all files from source\ to the src\ folder in the empty C project. Be sure to overwrite any existing files, and allow the project to build.
5) Attach the Atlys PROG port to your computer and switch the Atlys on.
6) Under “Xilinx Tools”, select Program FPGA. In the dialog box that appears, ensure that “ELF file to Initialize Block Ram” is set as bootloop and click Program.
7) Once the FPGA is programmed, right click on your project’s built binary (.elf file) and select Run As-> Launch on Hardware.
8) Connect your audio devices as wanted. You may swap the devices around during program execution. Be sure to set any volume controls on your playback device to a LOW level to prevent damage.
9) Use the onboard push buttons to perform the following operations:
• BTNR – Record a short period of audio and store it in memory. SW0 selects either LINE IN (up) or MIC (down) as the input source. LD0 will be illuminated while recording.
• BTNL – Play back the recorded audio data on both LINE OUT and HP OUT. LD1 will be illuminated while playing data back.
• BTND – Output a brief tone on both LINE OUT and HP OUT. The tone is played on the left, right, and then both stereo channels.
Overview
This project demonstrates the following audio processing capabilities of the Atlys:
• Recording audio data from the LINE IN and MIC jacks to memory
• Playing back recorded audio data over the LINE OUT and HP jacks
• Generating a square wave that is played on the left, right and then both stereo channels of the LINE OUT and HP jacks.
The project was designed using Xilinx EDK 13.2. It incorporates a custom AC’97 pcore that provides a software accessible interface with the codec hardware. This pcore is included with our BSB support packages so that it may easily be integrated into other EDK designs.
Running the Demo Application
The following equipment is required:
• Digilent Atlys Development Board
• Computer running Xilinx EDK 13.2 or newer
• 1 USB micro cable for programming
• One audio source with 3.5mm TRS wire
• One audio playback device with 3.5mm TRS wire
The following steps outline how to build the project in XPS and then execute the demo application on an Atlys. A basic understanding of Xilinx EDK is assumed. All file paths are given from the folder containing this document:
1) Open up project\system.xmp in XPS. Allow the tools to perform any necessary updates.
2) Export the Hardware design to SDK. This will take some time to complete.
3) Open up a new workspace in Xilinx SDK. If not done automatically, import the generated hardware profile.
4) Create an empty Xilinx C project and a standalone BSP. Copy all files from source\ to the src\ folder in the empty C project. Be sure to overwrite any existing files, and allow the project to build.
5) Attach the Atlys PROG port to your computer and switch the Atlys on.
6) Under “Xilinx Tools”, select Program FPGA. In the dialog box that appears, ensure that “ELF file to Initialize Block Ram” is set as bootloop and click Program.
7) Once the FPGA is programmed, right click on your project’s built binary (.elf file) and select Run As-> Launch on Hardware.
8) Connect your audio devices as wanted. You may swap the devices around during program execution. Be sure to set any volume controls on your playback device to a LOW level to prevent damage.
9) Use the onboard push buttons to perform the following operations:
• BTNR – Record a short period of audio and store it in memory. SW0 selects either LINE IN (up) or MIC (down) as the input source. LD0 will be illuminated while recording.
• BTNL – Play back the recorded audio data on both LINE OUT and HP OUT. LD1 will be illuminated while playing data back.
• BTND – Output a brief tone on both LINE OUT and HP OUT. The tone is played on the left, right, and then both stereo channels.