14-02-2011, 06:44 PM
Design and Implementation of Wireless Transceiver System Based on FPGA
The article describes a wireless data transmission and reciever system using FPGA and the RF chip. The system is meant for short distance communication only. The core of the system is a SOPC embedded in FPGA and the necessary peripheral circuits. The SOPC solution allows designers to embed soft-core of
the MCU to the generic FPGA. The SOPC technology mainly
refers to the chip-oriented system-level ASIC design of
computer technology as opposed to the ASIC design technology. The the burst mode transmission of wireless data under the control of FPGA is also introduced by this article. The design of wireless communication that is in the half duplex mode and involving burst mode was a challenge. The system can easily realize the wireless data transmission and also can work smoothly and steadily. The SOPC Builder and Quartus II are used for design of the entire system. An FPGA device belonging to the Cyclone I family of Altera is used in the project and the design is downloaded onto this FPGA. A very agile, and easy to debug is resulted from the project. simple structure, low-budget, low power consumption are the other advantages of the system.
The above SOPC design is based on IP (Intellectual
property) core and the main design means for it is the hardware description language which is carried out using the EDA tools.
Get the report here:
http://www.mediafire?hp62qqgg95c8h98
The article describes a wireless data transmission and reciever system using FPGA and the RF chip. The system is meant for short distance communication only. The core of the system is a SOPC embedded in FPGA and the necessary peripheral circuits. The SOPC solution allows designers to embed soft-core of
the MCU to the generic FPGA. The SOPC technology mainly
refers to the chip-oriented system-level ASIC design of
computer technology as opposed to the ASIC design technology. The the burst mode transmission of wireless data under the control of FPGA is also introduced by this article. The design of wireless communication that is in the half duplex mode and involving burst mode was a challenge. The system can easily realize the wireless data transmission and also can work smoothly and steadily. The SOPC Builder and Quartus II are used for design of the entire system. An FPGA device belonging to the Cyclone I family of Altera is used in the project and the design is downloaded onto this FPGA. A very agile, and easy to debug is resulted from the project. simple structure, low-budget, low power consumption are the other advantages of the system.
The above SOPC design is based on IP (Intellectual
property) core and the main design means for it is the hardware description language which is carried out using the EDA tools.
Get the report here:
http://www.mediafire?hp62qqgg95c8h98