05-03-2011, 05:10 PM
Wallace tree multipliers, when laid out in a rectangular shape, there arises a large amount of non-regularities and as a result, the there is a large amount of wasted area. But most of the wasted area in the multiplier layout can be saved by the method specified by itoh et al. This article compares and evaluates the different multiplier configurations with this wallace tree configuration. A comparison between the critical path and wiring overhead present in the case of the traditional and the modified wallace tree is presented here.
Wallace tree
A wallace tree is an efficient implementation of the hardware for multiplying two
integers. The three steps of the wallace tree are:
a) each bit of one of the arguments is multiplied(ie ANDed). This results i n^2 bits.
b)layers of full and half adders reduce the number of partial products to two.
c)The wiresare grouped in two numbers and then added by the conventional adders.
http://en.wikipediawiki/Wallace_tree
The projects also designs a wallace tree multiplier for multiplying 25X12 bits which is manufactured by using a 0.18μm process.
The motivation behinf the project is that fast three-dimensional computer graphics, high -speed floating-point processing are rapidly increasing demand and every DSP has dedicated multiplier units built into it. The Wallace tree architecture combined with the modified Booth recoding technique is used as it achieves high speed. It can add the partial products in parallel in a tree-like fashion.
Get the details here:
http://www.veechindex_files/Wallace%20Tree.pdf
Wallace tree
A wallace tree is an efficient implementation of the hardware for multiplying two
integers. The three steps of the wallace tree are:
a) each bit of one of the arguments is multiplied(ie ANDed). This results i n^2 bits.
b)layers of full and half adders reduce the number of partial products to two.
c)The wiresare grouped in two numbers and then added by the conventional adders.
http://en.wikipediawiki/Wallace_tree
The projects also designs a wallace tree multiplier for multiplying 25X12 bits which is manufactured by using a 0.18μm process.
The motivation behinf the project is that fast three-dimensional computer graphics, high -speed floating-point processing are rapidly increasing demand and every DSP has dedicated multiplier units built into it. The Wallace tree architecture combined with the modified Booth recoding technique is used as it achieves high speed. It can add the partial products in parallel in a tree-like fashion.
Get the details here:
http://www.veechindex_files/Wallace%20Tree.pdf