28-03-2011, 04:42 PM
PRESENTED BY:
Harish.B, Justinraj.G
[attachment=11197]
Low Power Consumption Using Dynamic Voltage Frequency Scaling[DVFS]
Abstract:
An effective mechanism for reducing processor power and energy.
In the last decade a lot of works have been done during the hardware and software implementation.
In this paper a proposed control loop of DVFS technique has been introduced.
Introduction:
In recent years the processors speed reaches Gigahertz, so the power dissipation increases rapidly in a level of the order of ten Watts
Processors consume a large energy around 50% of the overall consumed energy of computer systems
Today most digital circuits are constructed using CMOS circuits
Power dissipation in CMOS circuits is essential to findout the relation between power, supply voltage, and clock frequency
Pcmos = {Pdynamic+ Pstatic + Pshortcircuit}
Dynamic Power Dissipation
Pdynamic which is due to charging and discharging capacitors
Pdynamic α (CL Vdd2 fclk)
Pstatic which is due to reverse biased diodes
Pshortcircuit:
Pshortcircuit which is due to switching direct path between Vdd-GND
Pshortcircuit = Isc Vdd f
DEMERITS OF DVS:
The failure rate of a processor doubles every 10oC increase in the system
Increases the production cost of cooler
Shortens the battery or UPS life
It endangers the human body becoz it consumes 70-100W
MERITS OF DVFS:
By lowering the supply voltage, is effective in reducing power dissipation.
selected portions of the device are set to run at different voltages and frequencies
fclk α (Vdd- Vt)2/ Vdd)
The energy consumption of a program can be reduced by reducing the switching capacitance of each operation
PREVIOUS WORKS
Dynamic Voltage Scaling (DVS) is an effective low-power design for embedded real-time systems
“Supply voltage α processor speed”
Categories
◊Task arrival times,deadlines are known
◊Application or compiler support
◊ Target general purpose systems.
performs dynamic scaling based on their estimate of utilization for the next interval
ANALYSIS OF DVFS TECHNIQUE:
Power saving achievable by using variable Vdd
COMPONENTS FOR IMPLEMENTING DVFS :
Harish.B, Justinraj.G
[attachment=11197]
Low Power Consumption Using Dynamic Voltage Frequency Scaling[DVFS]
Abstract:
An effective mechanism for reducing processor power and energy.
In the last decade a lot of works have been done during the hardware and software implementation.
In this paper a proposed control loop of DVFS technique has been introduced.
Introduction:
In recent years the processors speed reaches Gigahertz, so the power dissipation increases rapidly in a level of the order of ten Watts
Processors consume a large energy around 50% of the overall consumed energy of computer systems
Today most digital circuits are constructed using CMOS circuits
Power dissipation in CMOS circuits is essential to findout the relation between power, supply voltage, and clock frequency
Pcmos = {Pdynamic+ Pstatic + Pshortcircuit}
Dynamic Power Dissipation
Pdynamic which is due to charging and discharging capacitors
Pdynamic α (CL Vdd2 fclk)
Pstatic which is due to reverse biased diodes
Pshortcircuit:
Pshortcircuit which is due to switching direct path between Vdd-GND
Pshortcircuit = Isc Vdd f
DEMERITS OF DVS:
The failure rate of a processor doubles every 10oC increase in the system
Increases the production cost of cooler
Shortens the battery or UPS life
It endangers the human body becoz it consumes 70-100W
MERITS OF DVFS:
By lowering the supply voltage, is effective in reducing power dissipation.
selected portions of the device are set to run at different voltages and frequencies
fclk α (Vdd- Vt)2/ Vdd)
The energy consumption of a program can be reduced by reducing the switching capacitance of each operation
PREVIOUS WORKS
Dynamic Voltage Scaling (DVS) is an effective low-power design for embedded real-time systems
“Supply voltage α processor speed”
Categories
◊Task arrival times,deadlines are known
◊Application or compiler support
◊ Target general purpose systems.
performs dynamic scaling based on their estimate of utilization for the next interval
ANALYSIS OF DVFS TECHNIQUE:
Power saving achievable by using variable Vdd
COMPONENTS FOR IMPLEMENTING DVFS :