19-04-2011, 03:02 PM
Presented by:
D.MURUGAN
[attachment=12396]
BZ-FAD
LOW-POWER LOW -AREA MULTIPLIER BASED ON SHIFT AND ADD ARCHITECHTURE
Multipliers
Multipliers are among the fundamental components of many digital systems
The largest contribution to the total power consumption in the multiplier is due to the generation of partial product
Among all the multipliers shift and add multipliers are the most commonly used ,due to its simplicity & relatively small area requirement
Multipliers
Higher radix multiplier are faster but consumes more power
In this work we propose some modifications to the conventional shift and add architecture
Main Sources of Switching Activity
1. Shifts of the B register,
2. Activity in the counter,
3. Activity in the adder,
4. Switching between '0' and A in the multiplexer,
5. Activity in the mux-select controlled by B(0),and
6. Shifts of the partial product (PP) register.
Proposed Low Power Multiplier: BZ-FAD
SHIFT OF B REGISTER:
In the traditional architecture, in each cycle B is shifted to the right at, so that its right bit appears at b(0).
If b(0) is 0,then ‘0’ is added with pp, else A is added with pp
In the proposed architecture, a multiplier(M1) with one encoded bus selector chooses the hot bit of B in each cycle.
A low power ring counter is used to select b(n) in nth cycle, which is wider than the binary counter used in conventional multiplier
Proposed Low Power Multiplier: BZ-FAD
Reducing the Switching Activity of the Adder
Reducing the unnecessary activities of the adder when b(0) is zero
Eliminating the unnecessary activities using bypass and feeder register
Removal of multiplexer.
In this work we use ripple carry adder,which has least transitions per addition among all the adders
Shift Of PP Register
In conventional multiplier multiplication is completed only by processing MSB
Notice that in Fig 2 for P Low, the lower half of the partial product, we use latches (for a k-bit multiplier).
In the 1st cycle LSB PP(0) of the procedure becomes finalised & stored in the right most bit of Plow
Ring counter
In a ring counter always a single '1' is moving from the right to the left. Therefore in each cycle only two flip-flops should be clocked. To reduce the switching activity of the counter, we
Once the Entrance signal becomes '1', the sample and datain lines of the latch are set to '1'.
The clock pulses come to the clock gating structure, propagate through the NAND gate, and go to the block cells via Clock-OUT, until the Exit signal becomes '1'.
Results and discussion
Ring counter
As seen in this diagram, the efficiency of the Hot Block architecture is more pronounced as the width of the ring counter increases
The clock gating structure used in ring counter is implemented using 18 transistor(10+4+4)
As the block size increases the area overhead decreases.
However, the larger the block size is, the higher the power consumption is.
D.MURUGAN
[attachment=12396]
BZ-FAD
LOW-POWER LOW -AREA MULTIPLIER BASED ON SHIFT AND ADD ARCHITECHTURE
Multipliers
Multipliers are among the fundamental components of many digital systems
The largest contribution to the total power consumption in the multiplier is due to the generation of partial product
Among all the multipliers shift and add multipliers are the most commonly used ,due to its simplicity & relatively small area requirement
Multipliers
Higher radix multiplier are faster but consumes more power
In this work we propose some modifications to the conventional shift and add architecture
Main Sources of Switching Activity
1. Shifts of the B register,
2. Activity in the counter,
3. Activity in the adder,
4. Switching between '0' and A in the multiplexer,
5. Activity in the mux-select controlled by B(0),and
6. Shifts of the partial product (PP) register.
Proposed Low Power Multiplier: BZ-FAD
SHIFT OF B REGISTER:
In the traditional architecture, in each cycle B is shifted to the right at, so that its right bit appears at b(0).
If b(0) is 0,then ‘0’ is added with pp, else A is added with pp
In the proposed architecture, a multiplier(M1) with one encoded bus selector chooses the hot bit of B in each cycle.
A low power ring counter is used to select b(n) in nth cycle, which is wider than the binary counter used in conventional multiplier
Proposed Low Power Multiplier: BZ-FAD
Reducing the Switching Activity of the Adder
Reducing the unnecessary activities of the adder when b(0) is zero
Eliminating the unnecessary activities using bypass and feeder register
Removal of multiplexer.
In this work we use ripple carry adder,which has least transitions per addition among all the adders
Shift Of PP Register
In conventional multiplier multiplication is completed only by processing MSB
Notice that in Fig 2 for P Low, the lower half of the partial product, we use latches (for a k-bit multiplier).
In the 1st cycle LSB PP(0) of the procedure becomes finalised & stored in the right most bit of Plow
Ring counter
In a ring counter always a single '1' is moving from the right to the left. Therefore in each cycle only two flip-flops should be clocked. To reduce the switching activity of the counter, we
Once the Entrance signal becomes '1', the sample and datain lines of the latch are set to '1'.
The clock pulses come to the clock gating structure, propagate through the NAND gate, and go to the block cells via Clock-OUT, until the Exit signal becomes '1'.
Results and discussion
Ring counter
As seen in this diagram, the efficiency of the Hot Block architecture is more pronounced as the width of the ring counter increases
The clock gating structure used in ring counter is implemented using 18 transistor(10+4+4)
As the block size increases the area overhead decreases.
However, the larger the block size is, the higher the power consumption is.