09-05-2011, 03:52 PM
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INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential “future” technology/device choices.
In these device structures, the short-channel effect is controlled by geometry, and the off-state leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length.
The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued.
As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.
PARTIALLY DEPLETED [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .
The device offers several advantages for performance/ power improvement:
1) reduced junction capacitance,
2) lower average threshold due to positive V BS during switching.
3) dynamic loading effects,in which the load device tends to be in high VT state during
switching
The performance comes at the cost of some design complexity resulting from the floating body of the device, such as
1) parasitic bipolar effect and
2) hysteretic VT variation.
Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.
In SRAM bitline structures, the aggregate parasitic bipolar effect of the unselected cells on the selected bitline disturbs the read/write operations and limits the number of cells that can be attached to a bitline pair
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.
Input/output waveforms&nMOS body voltage for a PD SOI CMOS inverter under “first switch” & “second switch” condition is shown above
The duty cycle, slew rate, and output load also affect the hysteretic behavior of the circuits. A higher duty cycle increases hysteretic behavior due to higher switching activity causing a gain or loss of body charge and less time for the
device to return/settle to its initial equilibrium state
SCALING Si FILM: FROM PD SOI TO FD SOI
The major benefits of scaling/thinning of the Si film are: 1) reduction of junction capacitance for performance improvement, 2) better short channel roll-off, and 3) better soft error rate (SER) due to less charge generation and collection volume.
In addition, the history effect (disparity between first switch and second switch) is also reduced. The reduced junction capacitance improves delays of both the first and second switches. However, for the second switch the reduced junction capacitance reduces the capacitive coupling between the drain and the body .The resulting decrease in the pre-switch body voltage for the second switch partially offsets the performance improvement.
Unfortunately, the thinning of Si film degrades the body resistance, rendering body contacts less effective and eventually useless .Self-heating becomes more severe. Furthermore, as the film thickness is scaled below 50nm,the device may become dynamically fully depleted (or quasi-depleted);the body would become fully depleted under certain bias conditions or during certain circuit-switching transients. This necessitates a unified PD|FD device model with smooth and seamless transitions among different modes of operation. Typically, this is modeled by varying the built-in potential between the body and source junction, thus changing the amount of body charges the body-to-source junction diode can sink for a given change in the body potential .The presence of dynamic full depletion also complicates the static timing methodology. The various body voltage bounds, established based on the assumption of partial depletion need to be extended to cover this new phenomenon. Notice that dynamic depletion tends to occur first in long-channel, low VT devices. For short channel devices, the proximity of the heavily doped “halo” regions to each other increases the effective body doping, and the device is less likely to be dynamically fully depleted. In a FD_SOI device, the channel depletion layer extends through the entire Si film. This significantly reduces the floating body effect (completely eliminating the floating-body effect with ultra-thin Si films). A raised source/drain structure is typically employed to overcome the large source/drain series resistance of the thin Si film. There are two approaches to achieve the desired VT. One can use the traditional dual P+/N+ poly-silicon with a highly doped channel. This approach has several drawbacks and limitations: a) VT would be sensitive to Si film thickness variation, b) high doping degrades the carrier mobility and results in junction edge leakage due to tunneling, and c) in devices with ultra-thin body, the amount of dopant required for the desired VT can not be realistically achieved. Excessively high body doping would turn the device into a “resistor” rather than a “transistor.” Consequently, the preferred and more scalable approach is to build an “undoped” channel with the desired VT set either by the source/drain halo or by the use of midgap gate materials. The use of undoped channel a) reduces the VT sensitivity to Si film thickness variation, b) reduces dopant fluctuation effect, c) reduces transverse electric field and impurity scattering, leading to higher mobility, and d) reduces band-to-band tunneling leakage at the junction edge.
The use of midgap gate materials may allow the use of a single electrode for both nMOSFETs and pMOSFETs.
As the Si film thickness is reduced, the gate has more control of the channel charges, and the subthreshold slope improves. The channel leakage in the device is limited by the Si film thickness and decreases as the film thickness is reduced. The fringing electric field from source/drain penetrates into the buried oxide underneath the channel, which causes back interface virtual biasing, resulting in increased Ioff and degraded subthreshold slope. This can be suppressed by thinning the buried oxide at the expense of larger junction capacitance to the substrate. The FD SOI technology is , in general, quite “transparent” for design migration and the challenge is primarily in technology development and manufacturing.
Gate Oxide Tunneling Leakage
As the gate oxide thickness is scaled to maintain gate control VT and performance,
gate insulator direct tunneling leakage increases. Nitrided oxide, which reduces the leakage by any order of magnitude , has been widely used in the industry to contain this leakage. Nevertheless, the oxide tunneling leakage increases by 2 5* for every 0.1 nm decrease in oxide thickness. This amounts to over a 30* increase per technology generation. On the contrary, the channel leakage increases by about 3-5 per technology generation. As such , the oxide tunneling leakage has quickly approached Ioff and will surpass Ioff at room temperature for oxide thickness around 1.0nm or below , thus becoming a serious concern for overall chip leakage.
Furthermore, at 1.0nm, the tunneling leaking for nitrided oxide reaches 100A/cm2,
while the traditional reliability limitation for silicon dioxide gate insulator leakage is 1.0A/cm2 .A recent study showed that, at 100 A/cm2 , static CMOS and domino circuits in bulk CMOS still exhibit “acceptable functionality and noise margin”.
The oxide tunneling current consists of several components. The electron tunneling
from the valence band (EVB) generates the substrate current in both nMOS and pMOS .This substrate current component is significantly less than the tunneling current between the gate and the channel, and its effect can usually be neglected in bulk CMOS .In PD SOI devices, however, this substrate current charges or discharges the body, thus changing VT and affecting circuit operation. As this gate-to-body tunneling current has a weaker temperature dependence than the channel current, and other leakage and body charging/discharging current components, its effect is more pronounced at lower temperature.
The detailed study on a 34-kb L1 directory SRAM showed that the presence of in the gate-to-body tunneling current resulted in much more significant degradation “write” operation compared with the “read” operation. On the other hand , the initial cycle parasitic bipolar disturb resulting from the aggregate effect of unselected cells in the same bitline was reduced.
The gate-to-body tunneling current increases the disparity between the first switch and the second switch.
In FD SOI and FinFET with ultra-thin body, the gate tunneling leakage is significantly reduced. This is because 1) in these, an undoped or very lightly doped body (channel) is used and the depletion charges essentially equal to zero, thus reducing the vertical electric field in the channel, and 2) the quantum confinement effect in ultra-thin Si film results in a broader inversion charge distribution and lower vertical electric field at the bottom of the inversion layer. Consequently, the gate tunneling leakage is reduced by about 3-4X.If a high-k gate dielectric such as HfO2 ,the reduction in gate current can exceed an order of magnitude as the increased physical thickness of the gate dielectric barrier makes the tunneling current more dependent upon the shape
of the potential well in Si. In general, scaling of the body thickness reduces the gate leakage current because the potential well becomes shallower. However, excessive scaling\thinning of body thickness below~5nm increases confinement of carriers toward the gate dielectric interface, and the gate current increases to approach that of the bulk devices. This may not be of concern since 5nm is close to the practical limit of body thickness in actual device technologies.
Self heating
The heat transfer is dominated by phonon transport in semiconductors and by electron transport in metals. The thermal conductivity of the buried oxide (1.4 W/m-.C) is about two orders of magnitude lower than that of Si (120 W/m-.C), giving rise to local self-heating in SOI devices. This is particularly a concern for devices that are “on” most or all the time (e.g., biasing elements, current source, current mirror, bleeder, etc.) and for circuits with high duty cycle and slow slew rate (such as clock distribution, I/O driver).
Scaling of the Si film degrades the thermal conductivity and increases the thermal resistance. In scaled SOI devices, both the channel length and Si film thickness are much smaller than the phonon mean free path for Si (~300 nm at room temperature), and the thermal conductivity is severely degraded due to phonon boundary scattering.
The thermal resistance increase is particularly significant for thinner Si film with thick buried oxide. As the Si film thickness is scaled further to approach the Phonon wavelength (~ tens of nm), the phonon confinement effect becomes significant. This is the mechanical/thermal analogy of the quantum confinement effect in electronic devices with an ultra-thin Si film. The boundary conditions change from the usual periodic boundary conditions for bulk materials to essentially zero displacements on the boundaries in SOI.
Soft Error Rate
The α-generated charges in SOI devices are substantially less than in bulk devices due to the presence of the buried oxide, and appreciable charge generation can only occur when an α-particle hits the channel region. While scaling of the device reduces the charge generation volume, the Qcrit also decreases due to a lower capacitance at the cell’s storage node and scaled VDD.
In a PD SOI device, the total charges accumulated at the cell storage node can be significantly higher than the α-generated charges due to the parasitic bipolar effect. For properly scaled PD SOI devices, the parasitic bipolar gain is reduced, and the resulting overall single-event-upset-induced failure rate is less than that of bulk silicon. Furthermore, scaling/thinning of the Si film reduces the charge generation volume and the base-emitter (body-source) junction area of the parasitic bipolar transistor, thus improving SER as well.
INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential “future” technology/device choices.
In these device structures, the short-channel effect is controlled by geometry, and the off-state leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length.
The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued.
As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.
PARTIALLY DEPLETED [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .
The device offers several advantages for performance/ power improvement:
1) reduced junction capacitance,
2) lower average threshold due to positive V BS during switching.
3) dynamic loading effects,in which the load device tends to be in high VT state during
switching
The performance comes at the cost of some design complexity resulting from the floating body of the device, such as
1) parasitic bipolar effect and
2) hysteretic VT variation.
Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.
In SRAM bitline structures, the aggregate parasitic bipolar effect of the unselected cells on the selected bitline disturbs the read/write operations and limits the number of cells that can be attached to a bitline pair
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.
Input/output waveforms&nMOS body voltage for a PD SOI CMOS inverter under “first switch” & “second switch” condition is shown above
The duty cycle, slew rate, and output load also affect the hysteretic behavior of the circuits. A higher duty cycle increases hysteretic behavior due to higher switching activity causing a gain or loss of body charge and less time for the
device to return/settle to its initial equilibrium state
SCALING Si FILM: FROM PD SOI TO FD SOI
The major benefits of scaling/thinning of the Si film are: 1) reduction of junction capacitance for performance improvement, 2) better short channel roll-off, and 3) better soft error rate (SER) due to less charge generation and collection volume.
In addition, the history effect (disparity between first switch and second switch) is also reduced. The reduced junction capacitance improves delays of both the first and second switches. However, for the second switch the reduced junction capacitance reduces the capacitive coupling between the drain and the body .The resulting decrease in the pre-switch body voltage for the second switch partially offsets the performance improvement.
Unfortunately, the thinning of Si film degrades the body resistance, rendering body contacts less effective and eventually useless .Self-heating becomes more severe. Furthermore, as the film thickness is scaled below 50nm,the device may become dynamically fully depleted (or quasi-depleted);the body would become fully depleted under certain bias conditions or during certain circuit-switching transients. This necessitates a unified PD|FD device model with smooth and seamless transitions among different modes of operation. Typically, this is modeled by varying the built-in potential between the body and source junction, thus changing the amount of body charges the body-to-source junction diode can sink for a given change in the body potential .The presence of dynamic full depletion also complicates the static timing methodology. The various body voltage bounds, established based on the assumption of partial depletion need to be extended to cover this new phenomenon. Notice that dynamic depletion tends to occur first in long-channel, low VT devices. For short channel devices, the proximity of the heavily doped “halo” regions to each other increases the effective body doping, and the device is less likely to be dynamically fully depleted. In a FD_SOI device, the channel depletion layer extends through the entire Si film. This significantly reduces the floating body effect (completely eliminating the floating-body effect with ultra-thin Si films). A raised source/drain structure is typically employed to overcome the large source/drain series resistance of the thin Si film. There are two approaches to achieve the desired VT. One can use the traditional dual P+/N+ poly-silicon with a highly doped channel. This approach has several drawbacks and limitations: a) VT would be sensitive to Si film thickness variation, b) high doping degrades the carrier mobility and results in junction edge leakage due to tunneling, and c) in devices with ultra-thin body, the amount of dopant required for the desired VT can not be realistically achieved. Excessively high body doping would turn the device into a “resistor” rather than a “transistor.” Consequently, the preferred and more scalable approach is to build an “undoped” channel with the desired VT set either by the source/drain halo or by the use of midgap gate materials. The use of undoped channel a) reduces the VT sensitivity to Si film thickness variation, b) reduces dopant fluctuation effect, c) reduces transverse electric field and impurity scattering, leading to higher mobility, and d) reduces band-to-band tunneling leakage at the junction edge.
The use of midgap gate materials may allow the use of a single electrode for both nMOSFETs and pMOSFETs.
As the Si film thickness is reduced, the gate has more control of the channel charges, and the subthreshold slope improves. The channel leakage in the device is limited by the Si film thickness and decreases as the film thickness is reduced. The fringing electric field from source/drain penetrates into the buried oxide underneath the channel, which causes back interface virtual biasing, resulting in increased Ioff and degraded subthreshold slope. This can be suppressed by thinning the buried oxide at the expense of larger junction capacitance to the substrate. The FD SOI technology is , in general, quite “transparent” for design migration and the challenge is primarily in technology development and manufacturing.
Gate Oxide Tunneling Leakage
As the gate oxide thickness is scaled to maintain gate control VT and performance,
gate insulator direct tunneling leakage increases. Nitrided oxide, which reduces the leakage by any order of magnitude , has been widely used in the industry to contain this leakage. Nevertheless, the oxide tunneling leakage increases by 2 5* for every 0.1 nm decrease in oxide thickness. This amounts to over a 30* increase per technology generation. On the contrary, the channel leakage increases by about 3-5 per technology generation. As such , the oxide tunneling leakage has quickly approached Ioff and will surpass Ioff at room temperature for oxide thickness around 1.0nm or below , thus becoming a serious concern for overall chip leakage.
Furthermore, at 1.0nm, the tunneling leaking for nitrided oxide reaches 100A/cm2,
while the traditional reliability limitation for silicon dioxide gate insulator leakage is 1.0A/cm2 .A recent study showed that, at 100 A/cm2 , static CMOS and domino circuits in bulk CMOS still exhibit “acceptable functionality and noise margin”.
The oxide tunneling current consists of several components. The electron tunneling
from the valence band (EVB) generates the substrate current in both nMOS and pMOS .This substrate current component is significantly less than the tunneling current between the gate and the channel, and its effect can usually be neglected in bulk CMOS .In PD SOI devices, however, this substrate current charges or discharges the body, thus changing VT and affecting circuit operation. As this gate-to-body tunneling current has a weaker temperature dependence than the channel current, and other leakage and body charging/discharging current components, its effect is more pronounced at lower temperature.
The detailed study on a 34-kb L1 directory SRAM showed that the presence of in the gate-to-body tunneling current resulted in much more significant degradation “write” operation compared with the “read” operation. On the other hand , the initial cycle parasitic bipolar disturb resulting from the aggregate effect of unselected cells in the same bitline was reduced.
The gate-to-body tunneling current increases the disparity between the first switch and the second switch.
In FD SOI and FinFET with ultra-thin body, the gate tunneling leakage is significantly reduced. This is because 1) in these, an undoped or very lightly doped body (channel) is used and the depletion charges essentially equal to zero, thus reducing the vertical electric field in the channel, and 2) the quantum confinement effect in ultra-thin Si film results in a broader inversion charge distribution and lower vertical electric field at the bottom of the inversion layer. Consequently, the gate tunneling leakage is reduced by about 3-4X.If a high-k gate dielectric such as HfO2 ,the reduction in gate current can exceed an order of magnitude as the increased physical thickness of the gate dielectric barrier makes the tunneling current more dependent upon the shape
of the potential well in Si. In general, scaling of the body thickness reduces the gate leakage current because the potential well becomes shallower. However, excessive scaling\thinning of body thickness below~5nm increases confinement of carriers toward the gate dielectric interface, and the gate current increases to approach that of the bulk devices. This may not be of concern since 5nm is close to the practical limit of body thickness in actual device technologies.
Self heating
The heat transfer is dominated by phonon transport in semiconductors and by electron transport in metals. The thermal conductivity of the buried oxide (1.4 W/m-.C) is about two orders of magnitude lower than that of Si (120 W/m-.C), giving rise to local self-heating in SOI devices. This is particularly a concern for devices that are “on” most or all the time (e.g., biasing elements, current source, current mirror, bleeder, etc.) and for circuits with high duty cycle and slow slew rate (such as clock distribution, I/O driver).
Scaling of the Si film degrades the thermal conductivity and increases the thermal resistance. In scaled SOI devices, both the channel length and Si film thickness are much smaller than the phonon mean free path for Si (~300 nm at room temperature), and the thermal conductivity is severely degraded due to phonon boundary scattering.
The thermal resistance increase is particularly significant for thinner Si film with thick buried oxide. As the Si film thickness is scaled further to approach the Phonon wavelength (~ tens of nm), the phonon confinement effect becomes significant. This is the mechanical/thermal analogy of the quantum confinement effect in electronic devices with an ultra-thin Si film. The boundary conditions change from the usual periodic boundary conditions for bulk materials to essentially zero displacements on the boundaries in SOI.
Soft Error Rate
The α-generated charges in SOI devices are substantially less than in bulk devices due to the presence of the buried oxide, and appreciable charge generation can only occur when an α-particle hits the channel region. While scaling of the device reduces the charge generation volume, the Qcrit also decreases due to a lower capacitance at the cell’s storage node and scaled VDD.
In a PD SOI device, the total charges accumulated at the cell storage node can be significantly higher than the α-generated charges due to the parasitic bipolar effect. For properly scaled PD SOI devices, the parasitic bipolar gain is reduced, and the resulting overall single-event-upset-induced failure rate is less than that of bulk silicon. Furthermore, scaling/thinning of the Si film reduces the charge generation volume and the base-emitter (body-source) junction area of the parasitic bipolar transistor, thus improving SER as well.