19-05-2011, 03:36 PM
Floating-Point FPGA: Architecture and Modeling
An architecture for a reconfigurable device that is specifically optimized for floating-point applications is described in this article. The control logic and bit-oriented operations are implemented by the fine grained units and the parameterized and reconfigurable word-based lookup tables etc are implemented by the coarse grained units. These implement the lookup tables and the floating point operations as well as to implemen the data paths. the virtual embedded block scheme is described which is sued fo facilitate the comparison with the existing FPGA devices. Thus, embedded blocks are modelled by using the existing FPGA development tools. current FPGA devices employ an islandstyle fine-grained architecturein which there are additional heterogenous blocks such as block RAMs and multipliers. This article describes the architecture of the FPGA that is optimised for floating point applications. DSP, control, high-performance computing are some of the areas that can utilise this FPGA. The usage of multiple granularity has the advantages of improved speed, density, and less power than the conventional FPGAs. The VEB(virtual embeded blocks) methodology allows modeling of FPGA architectures with embedded blocks and comparisons with commercial FPGAs. VEBs are created from the reconfigurable fabric of an existing FPGA so that the area, placement and delay can be included in the FPGA fabric. The simulations and tests have shown that using the proposed architecture , four times improvement in speed and 25 times reduction in area can be achieved compared with the traditional FPGA device.
get the report here:
http://www.mediafirefile/2fwrlalprgvma5d...deling.pdf
An architecture for a reconfigurable device that is specifically optimized for floating-point applications is described in this article. The control logic and bit-oriented operations are implemented by the fine grained units and the parameterized and reconfigurable word-based lookup tables etc are implemented by the coarse grained units. These implement the lookup tables and the floating point operations as well as to implemen the data paths. the virtual embedded block scheme is described which is sued fo facilitate the comparison with the existing FPGA devices. Thus, embedded blocks are modelled by using the existing FPGA development tools. current FPGA devices employ an islandstyle fine-grained architecturein which there are additional heterogenous blocks such as block RAMs and multipliers. This article describes the architecture of the FPGA that is optimised for floating point applications. DSP, control, high-performance computing are some of the areas that can utilise this FPGA. The usage of multiple granularity has the advantages of improved speed, density, and less power than the conventional FPGAs. The VEB(virtual embeded blocks) methodology allows modeling of FPGA architectures with embedded blocks and comparisons with commercial FPGAs. VEBs are created from the reconfigurable fabric of an existing FPGA so that the area, placement and delay can be included in the FPGA fabric. The simulations and tests have shown that using the proposed architecture , four times improvement in speed and 25 times reduction in area can be achieved compared with the traditional FPGA device.
get the report here:
http://www.mediafirefile/2fwrlalprgvma5d...deling.pdf