20-05-2011, 08:12 AM
Implementation of a Multi-Processing Architecture Approach on FPGA
Implementation of a Multi-Processing Architecture Approach on FPGA
In the present FPGA devices, the major objectives have been high performance, low technology access cost and application code reusability. An "architectured FPGA" approach is presented in this article which can be useful for the embedded system application implementations. Image processing has been addressed here as the first application doman and an FPGA implementation for the image processing applications has been presented in the article. High performance and highly integrated implementation solutions are required by the embedded image or signal processing systems . smart cameras, airborne radar, airospace and defense etc. can be the domains of interest. The advantages such as limited power consumption, limited size, high processing power, limited production volumes must be concilated. a strong increase in the complexity of algorithms is required by the customer demand to move from simple display systems to intelligent systems to obtain the important information from the signal or an image.
But today, massively parallel architectures are not implemented by the general
purpose COTS microprocessors nor general purpose COTS DSPs. As a consequense, they are not able to take the complete advantage of the increase in the complexity of the integrated circuits in accordance with the moore’s law. new architectural products are expected to have increased processing power but they are not considered mature enough for the aerospace and defense applications. FPGA requires much less development costs but they have limited processing power. Thus, a good compromise between microprocessors or DSP and ASIC is provided by the FPGA.
Get the report here:
http://www.mediafirefile/5f9a11ebvbysbby...20FPGA.pdf