20-06-2011, 09:53 AM
Presented by
Mary Deepti Pulukuri
[attachment=14112]
1. Design Implementation:
By implementing the above design on paper I found that the overflow bit is not required. The overflow bit shifts into the product register. To implement the 32 bit-register I had two initialized product registers, preg1 and preg2. Preg1 has the multiplier in the least significant 32-bit positions and the most significant 32-bits are zeros. Preg2 has the multiplicand in the most significant 32-bit positions and the least significant 32-bits are zeros. If the least significant bit of the multiplier product register, preg1, is a ‘1’, then the multiplicand product register, preg2, is added to the multiplier product register and the result stored in the multiplier product register is shifted right by one bit. If the least significant bit of the multiplier product register is a ‘0’, the bits in the multiplier product register are right shifted by one bit without the addition of the multiplicand product register. This is done 32 times. The result in the multiplier product register after 32 clock cycles is the final product.
The code for the design described above is written in VHDL as shown below:
library IEEE;
Mary Deepti Pulukuri
[attachment=14112]
1. Design Implementation:
By implementing the above design on paper I found that the overflow bit is not required. The overflow bit shifts into the product register. To implement the 32 bit-register I had two initialized product registers, preg1 and preg2. Preg1 has the multiplier in the least significant 32-bit positions and the most significant 32-bits are zeros. Preg2 has the multiplicand in the most significant 32-bit positions and the least significant 32-bits are zeros. If the least significant bit of the multiplier product register, preg1, is a ‘1’, then the multiplicand product register, preg2, is added to the multiplier product register and the result stored in the multiplier product register is shifted right by one bit. If the least significant bit of the multiplier product register is a ‘0’, the bits in the multiplier product register are right shifted by one bit without the addition of the multiplicand product register. This is done 32 times. The result in the multiplier product register after 32 clock cycles is the final product.
The code for the design described above is written in VHDL as shown below:
library IEEE;
Code:
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mul is
Port ( mplier,mcand: in std_logic_vector(31 downto 0);
clk,start,reset:in std_logic;
done:out std_logic;
product: out std_logic_vector(63 downto 0));
end mul;
architecture behavioral of mul is
signal count: integer range 0 to 33;
signal preg1,preg2: std_logic_vector(63 downto 0);
begin
product <= preg1(63 downto 0);
process(clk,reset)
variable t: std_logic_vector(63 downto 0);
begin
if (reset='1') then
count<=0;
preg1<="0000000000000000000000000000000000000000000000000000000000000000";
preg2<="0000000000000000000000000000000000000000000000000000000000000000";
elsif (clk'event and clk ='1') then
case count is
when 0 =>
if (start='1') then
preg1<="00000000000000000000000000000000" & mplier;
preg2<=mcand & "00000000000000000000000000000000";
count <= 1;
end if;
when 1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32 =>
if (preg1(0)='1') then
t:= preg1 + preg2;
t:='0' & t(63 downto 1);
preg1<=t;
count<=count + 1;
else --if (preg1(0) ='0') then
preg1<='0' & preg1(63 downto 1);
count<=count+1;
end if;
when 33 =>
count<=0;
end case;
end if;
end process;
done<='1' when count=33 else '0';
end behavioral;