09-07-2011, 03:00 PM
[attachment=14402]
INTRODUCTION
The continued scaling of integrated circuit fabrication technology will
dramatically affect the architecture of future computing systems. Scaling will
make computation cheaper, smaller, and lower power, thus enabling more
sophisticated computation in a growing number of embedded applications. This
spread of low-cost, low power computing can easily be seen in today’s wired
(e.g. gigabit Ethernet or DSL) and wireless communication devices, gaming
consoles, and handheld PDAs. These new applications have different
characteristics from today’s standard workloads, often containing highly data-
parallel streaming behavior. While the applications will demand ever-growing
compute performance, power (ops/W) and computational efficiency (ops/$)
are also paramount; therefore, designers have created narrowly focused
custom silicon solutions to meet these needs.
However, the scaling of process technologies makes the construction of
custom solutions increasingly difficult due to the increasing complexity of the
desired devices. While designer productivity has improved over time, and
technologies like system-on-a-chip help to manage complexity, each generation
of complex machines is more expensive to design than the previous one. High
non-recurring fabrication costs (e.g. mask generation) and long chip
manufacturing delays mean that designs must be all the more carefully
validated, further increasing the design costs. Thus, these large complex chips
are only cost-effective if they can be sold in large volumes. This need for a large
market runs counter to the drive for efficient, narrowly- focused, custom
hardware solutions.
To fill the need for widely applicable computing designs, a number of
more general-purpose processors are targeted at a class of problems, rather
than at specific applications. Tri-media, Equator, Mpact, IRAM, and many other
projects are all attempts to create general purpose computing engine for multi-
media applications. However, these attempts to create more universal
computing elements have some limitations. First, these machines have been
optimized for applications where the parallelism can be expressed at the
instruction level using either VLIW or vector engines. However, they would not
be very efficient for applications that lacked parallelism at this level, but had,
for example, thread level parallelism. Second, their globally shared resource
models (shared multi-ported registers and memory) will be increasingly
difficult to implement in future technologies in which on-chip communication
costs are appreciable. Finally, since these machines are generally compromise
solutions between true signal processing engines and general-purpose
processors, their efficiency at doing either task suffers.
On the other hand, the need for scalable architectures has also led to
proposals for modular, explicitly parallel architectures that typically consist of
a number of processing elements and memories on a die connected together by
a network. The modular nature of these designs ensures that wire lengths
shrink as technologies improve, allowing wire and gate delays to scale at
roughly the same rate. Additionally, the replication consumes the growing
number of transistors. The multiple processing elements take advantage of
both instruction-level and thread-level parallelism. One of the most prominent
architectures in this class is the MIT Raw project, which focuses on the
development of compiler technologies that take advantage of exposed low-level
hardware.
Smart Memories combines the benefits of both approaches to create a
partitioned, explicitly parallel, reconfigurable architecture for use as a future
universal computing element. Since different application spaces naturally have
different communication patterns and memory needs, finding a single topology
that fits well with all applications is very difficult. Rather than trying to find a
general solution for all applications, we tailor the appearance of the on-chip
memory, interconnection network, and processing elements to better match
the application requirements. We leverage the fact that long wires in current
(and future) VLSI chips require active repeater insertion for minimum delay.
The presence of repeaters means that adding some reconfigurable logic to
these wires will only modestly impact their performance. Reconfiguration at
this level leads to coarser-grained configurability than previous reconfigurable
architectures, most of which were at least in part based on FPGA
implementations. Compared to these systems, Smart Memories trades away
some flexibility for lower overheads, more familiar programming models, and
higher efficiency.
SMART MEMORIES OVERVIEW
At the highest level, a Smart Memories chip is a modular computer. It
contains an array of processor tiles and on-die DRAM memories connected by a
packet-based, dynamically-routed network (Figure 1). The network also
connects to high-speed links on the pins of the chip to allow for the
construction of multi-chip systems. Most of the initial hardware design works
in the Smart Memories project has been on the processor tile design and
evaluation, so this paper focuses on these aspects.
INTRODUCTION
The continued scaling of integrated circuit fabrication technology will
dramatically affect the architecture of future computing systems. Scaling will
make computation cheaper, smaller, and lower power, thus enabling more
sophisticated computation in a growing number of embedded applications. This
spread of low-cost, low power computing can easily be seen in today’s wired
(e.g. gigabit Ethernet or DSL) and wireless communication devices, gaming
consoles, and handheld PDAs. These new applications have different
characteristics from today’s standard workloads, often containing highly data-
parallel streaming behavior. While the applications will demand ever-growing
compute performance, power (ops/W) and computational efficiency (ops/$)
are also paramount; therefore, designers have created narrowly focused
custom silicon solutions to meet these needs.
However, the scaling of process technologies makes the construction of
custom solutions increasingly difficult due to the increasing complexity of the
desired devices. While designer productivity has improved over time, and
technologies like system-on-a-chip help to manage complexity, each generation
of complex machines is more expensive to design than the previous one. High
non-recurring fabrication costs (e.g. mask generation) and long chip
manufacturing delays mean that designs must be all the more carefully
validated, further increasing the design costs. Thus, these large complex chips
are only cost-effective if they can be sold in large volumes. This need for a large
market runs counter to the drive for efficient, narrowly- focused, custom
hardware solutions.
To fill the need for widely applicable computing designs, a number of
more general-purpose processors are targeted at a class of problems, rather
than at specific applications. Tri-media, Equator, Mpact, IRAM, and many other
projects are all attempts to create general purpose computing engine for multi-
media applications. However, these attempts to create more universal
computing elements have some limitations. First, these machines have been
optimized for applications where the parallelism can be expressed at the
instruction level using either VLIW or vector engines. However, they would not
be very efficient for applications that lacked parallelism at this level, but had,
for example, thread level parallelism. Second, their globally shared resource
models (shared multi-ported registers and memory) will be increasingly
difficult to implement in future technologies in which on-chip communication
costs are appreciable. Finally, since these machines are generally compromise
solutions between true signal processing engines and general-purpose
processors, their efficiency at doing either task suffers.
On the other hand, the need for scalable architectures has also led to
proposals for modular, explicitly parallel architectures that typically consist of
a number of processing elements and memories on a die connected together by
a network. The modular nature of these designs ensures that wire lengths
shrink as technologies improve, allowing wire and gate delays to scale at
roughly the same rate. Additionally, the replication consumes the growing
number of transistors. The multiple processing elements take advantage of
both instruction-level and thread-level parallelism. One of the most prominent
architectures in this class is the MIT Raw project, which focuses on the
development of compiler technologies that take advantage of exposed low-level
hardware.
Smart Memories combines the benefits of both approaches to create a
partitioned, explicitly parallel, reconfigurable architecture for use as a future
universal computing element. Since different application spaces naturally have
different communication patterns and memory needs, finding a single topology
that fits well with all applications is very difficult. Rather than trying to find a
general solution for all applications, we tailor the appearance of the on-chip
memory, interconnection network, and processing elements to better match
the application requirements. We leverage the fact that long wires in current
(and future) VLSI chips require active repeater insertion for minimum delay.
The presence of repeaters means that adding some reconfigurable logic to
these wires will only modestly impact their performance. Reconfiguration at
this level leads to coarser-grained configurability than previous reconfigurable
architectures, most of which were at least in part based on FPGA
implementations. Compared to these systems, Smart Memories trades away
some flexibility for lower overheads, more familiar programming models, and
higher efficiency.
SMART MEMORIES OVERVIEW
At the highest level, a Smart Memories chip is a modular computer. It
contains an array of processor tiles and on-die DRAM memories connected by a
packet-based, dynamically-routed network (Figure 1). The network also
connects to high-speed links on the pins of the chip to allow for the
construction of multi-chip systems. Most of the initial hardware design works
in the Smart Memories project has been on the processor tile design and
evaluation, so this paper focuses on these aspects.