11-01-2012, 04:00 PM
Reconfigurable Data Acquisition System for Weather Radar Applications
[attachment=15992]
I. INTRODUCTION
Data acquisition systems are an integral part of radar
applications [1]. A weather radar transmits radio frequency
signals and acquires meteorological information based on
the echo of such signals from particles in the atmosphere.
Data acquisition systems must digitize such backscatter, and
perform various processing tasks to cast the raw data into
an intelligible and meaningful format
III. DATA ACQUISITION SYSTEM ARCHITECTURE
A. Hardware Architecture
Figure 1 gives the data acquisition system architecture. For
clarity, only major components are shown. Two Altera Stratix
EP1S40 FPGAs [4] form the main processing modules of this
architecture. These parts each contain 41,250 logic elements,
abundant internal memory (over 3 Mbits), and dedicated multiplier
circuitry. These FPGAs are controlled and supervised
by an Atmel AT91RM9200 microcontroller [5].
II. MOTIVATION
The DCAS application presents some unique challenges
in data acquisition. Previous generations of data collection
systems for weather radar applications could be categorized
into two groups: those used for high performance research
applications, and those intended for large operational weather
radars such as NEXRAD [2]. Members of the first family
are characterized by high data rates, and a relatively large
amount of flexibility for the radar system designer
A. Hardware Architecture
Figure 1 gives the data acquisition system architecture. For
clarity, only major components are shown. Two Altera Stratix
EP1S40 FPGAs [4] form the main processing modules of this
architecture. These parts each contain 41,250 logic elements,
abundant internal memory (over 3 Mbits), and dedicated multiplier
circuitry. These FPGAs are controlled and supervised
by an Atmel AT91RM9200 microcontroller
V. SUMMARY
This research project has developed a single-card reconfigurable
data acquisition architecture for DCAS, a hazardous
weather prediction radar system. The presence of high-density,
high-performance FPGAs as processing elements, a microcontroller
acting as the master control, and a variety of contemporary
high-speed communication interfaces facilitate real-time
acquisition, processing and distribution of radar data. Essential
features such as remote-host based control and reconfiguration
of the system has been successfully implemented.
[attachment=15992]
I. INTRODUCTION
Data acquisition systems are an integral part of radar
applications [1]. A weather radar transmits radio frequency
signals and acquires meteorological information based on
the echo of such signals from particles in the atmosphere.
Data acquisition systems must digitize such backscatter, and
perform various processing tasks to cast the raw data into
an intelligible and meaningful format
III. DATA ACQUISITION SYSTEM ARCHITECTURE
A. Hardware Architecture
Figure 1 gives the data acquisition system architecture. For
clarity, only major components are shown. Two Altera Stratix
EP1S40 FPGAs [4] form the main processing modules of this
architecture. These parts each contain 41,250 logic elements,
abundant internal memory (over 3 Mbits), and dedicated multiplier
circuitry. These FPGAs are controlled and supervised
by an Atmel AT91RM9200 microcontroller [5].
II. MOTIVATION
The DCAS application presents some unique challenges
in data acquisition. Previous generations of data collection
systems for weather radar applications could be categorized
into two groups: those used for high performance research
applications, and those intended for large operational weather
radars such as NEXRAD [2]. Members of the first family
are characterized by high data rates, and a relatively large
amount of flexibility for the radar system designer
A. Hardware Architecture
Figure 1 gives the data acquisition system architecture. For
clarity, only major components are shown. Two Altera Stratix
EP1S40 FPGAs [4] form the main processing modules of this
architecture. These parts each contain 41,250 logic elements,
abundant internal memory (over 3 Mbits), and dedicated multiplier
circuitry. These FPGAs are controlled and supervised
by an Atmel AT91RM9200 microcontroller
V. SUMMARY
This research project has developed a single-card reconfigurable
data acquisition architecture for DCAS, a hazardous
weather prediction radar system. The presence of high-density,
high-performance FPGAs as processing elements, a microcontroller
acting as the master control, and a variety of contemporary
high-speed communication interfaces facilitate real-time
acquisition, processing and distribution of radar data. Essential
features such as remote-host based control and reconfiguration
of the system has been successfully implemented.