20-03-2012, 04:53 PM
DSP ARCHITECTURES FOR SYSTEM DESIGN
[attachment=18663]
INTRODUCTION:
With the advent of Digital Signal Processors one can easily classify processors as follows. A General Purpose
Processor (GPP) is very efficient in data manipulation. A Digital Signal Processor (DSP) is designed specially
to efficiently perform mathematical calculation. DSPs have their architectures optimized so that all the
operations it undertakes are finished within as low clock cycles as possible. A GPP cannot perform well for
DSP applications. DSP based applications demand a lot of number crunching, very high data bandwidth, real
time constraints, attention to subtle numeric effects (in fixed-point implementations), and specialized
peripherals/interfaces.
A Digital Signal Processor’s average speed performance is far better than a corresponding GPP clocked by
the same clock. Thus any GPP architecture would want to move towards DSP architecture. A general trend
shows that GPP Architecture approaches to DSP:
· Initially we had Baseline GPPs (moderate performance, no DSP features) like the 8085,8086,80386 etc. These
low/moderate performance GPPs with no DSP features perform poorly on DSP tasks because they have poor
multiplication throughput, limited memory bandwidth, loop overhead, address generation overhead. Also,
being fixed- point processors they lack hardware to support fast overflow protection, convergent rounding,
etc.
· Then there were high-performance GPPs with few/no DSP-oriented features like Pentium (P54C). These
processors performed well on DSP tasks as they had high clock rates (200+ MHz; 2- 5 X those of typical
DSPs), multiplication and fast arithmetic operations, Good memory bandwidth, Loop overhead reduced via
branch prediction, and floating point arithmetic block included. However, dynamic features complicate
optimization of DSP code and make real- time development difficult.
· Then there were GPPs with major DSP-oriented features. For example, Intel MMX Pentium (P55C). These
processors achieve outstanding DSP performance by combining the features of “conventional” highperformance
GPPs with new SIMD (single instruction multiple data path) capabilities by partition existing
data path (or adding a new partitioned data path), Multiple operations/cycle on small data types (e.g., 4
multiplies), Single-cycle operations on various fixed- point data types.
In addition there were DSP co-processors like ARM Piccolo co-processor(for ARM7 designs), which gave
better performance on DSP tasks as compared to their corresponding processor systems without a coprocessor.
Thus it is observed a Digital Signal Processor is very important block not only for DSP applications but also
for General Purpose Processors.
DSP ISSUES
2.1 REAL TIME & OFFLINE PROCESSES
In off-line processing, the entire input signal resides in the memory at the same time or is available for the
processing. In real-time processing, the output signal is to be produced at the same time that the input signal is
being acquired. Here the entire processing that needs to be done on the input samples, should be completed so
fast such that the new samples or group of samples that arrive are not
lost or output unprocessed. This requires very high processing
speeds, which are achieved by DSPs while difficult to achieve in
GPPs.
2.2 MAC UNIT
The most typical feature that differentiates a DSP from any GPP is
the Multiply and ACcumulate unit. All DSP Algorithms would
require some form of the Multiplication and Accumulation Operation
of the form
å X1(k,n) X2(k,n) = Y(n).
Thus arises the need to multiply and add the product to the previous
result as fast as possible, ideally single clock. The GPPs would not
have a multiply instruction ready for use, and even if it were present,
would take lot of cycles to complete a single multiplication.
A DSP has a specialized block called the MAC unit (Multiply and
Accumulate Unit) that will multiply the 2 input operands and add
the result to a register that has stored all previous results. The
figure 1 shows the simplest way to implement the MAC.
2.3 BUS ARCHITECTURES
Typically a GPP would have VonNeuman Architecture while a DSP would have Harvard Architecture.
VonNeuman architecture has a single data bus and an address bus and same memory where the data and
instructions are stored. Here instruction
fetching would cause a bottleneck. Refer
figure 2a. Harvard architecture separates
the data and address memories and so the
busses to access them are different too.
This allows instructions and data to be
processed separately and concurrently for
improved throughput and thus performance.
Refer figure 2b.
[attachment=18663]
INTRODUCTION:
With the advent of Digital Signal Processors one can easily classify processors as follows. A General Purpose
Processor (GPP) is very efficient in data manipulation. A Digital Signal Processor (DSP) is designed specially
to efficiently perform mathematical calculation. DSPs have their architectures optimized so that all the
operations it undertakes are finished within as low clock cycles as possible. A GPP cannot perform well for
DSP applications. DSP based applications demand a lot of number crunching, very high data bandwidth, real
time constraints, attention to subtle numeric effects (in fixed-point implementations), and specialized
peripherals/interfaces.
A Digital Signal Processor’s average speed performance is far better than a corresponding GPP clocked by
the same clock. Thus any GPP architecture would want to move towards DSP architecture. A general trend
shows that GPP Architecture approaches to DSP:
· Initially we had Baseline GPPs (moderate performance, no DSP features) like the 8085,8086,80386 etc. These
low/moderate performance GPPs with no DSP features perform poorly on DSP tasks because they have poor
multiplication throughput, limited memory bandwidth, loop overhead, address generation overhead. Also,
being fixed- point processors they lack hardware to support fast overflow protection, convergent rounding,
etc.
· Then there were high-performance GPPs with few/no DSP-oriented features like Pentium (P54C). These
processors performed well on DSP tasks as they had high clock rates (200+ MHz; 2- 5 X those of typical
DSPs), multiplication and fast arithmetic operations, Good memory bandwidth, Loop overhead reduced via
branch prediction, and floating point arithmetic block included. However, dynamic features complicate
optimization of DSP code and make real- time development difficult.
· Then there were GPPs with major DSP-oriented features. For example, Intel MMX Pentium (P55C). These
processors achieve outstanding DSP performance by combining the features of “conventional” highperformance
GPPs with new SIMD (single instruction multiple data path) capabilities by partition existing
data path (or adding a new partitioned data path), Multiple operations/cycle on small data types (e.g., 4
multiplies), Single-cycle operations on various fixed- point data types.
In addition there were DSP co-processors like ARM Piccolo co-processor(for ARM7 designs), which gave
better performance on DSP tasks as compared to their corresponding processor systems without a coprocessor.
Thus it is observed a Digital Signal Processor is very important block not only for DSP applications but also
for General Purpose Processors.
DSP ISSUES
2.1 REAL TIME & OFFLINE PROCESSES
In off-line processing, the entire input signal resides in the memory at the same time or is available for the
processing. In real-time processing, the output signal is to be produced at the same time that the input signal is
being acquired. Here the entire processing that needs to be done on the input samples, should be completed so
fast such that the new samples or group of samples that arrive are not
lost or output unprocessed. This requires very high processing
speeds, which are achieved by DSPs while difficult to achieve in
GPPs.
2.2 MAC UNIT
The most typical feature that differentiates a DSP from any GPP is
the Multiply and ACcumulate unit. All DSP Algorithms would
require some form of the Multiplication and Accumulation Operation
of the form
å X1(k,n) X2(k,n) = Y(n).
Thus arises the need to multiply and add the product to the previous
result as fast as possible, ideally single clock. The GPPs would not
have a multiply instruction ready for use, and even if it were present,
would take lot of cycles to complete a single multiplication.
A DSP has a specialized block called the MAC unit (Multiply and
Accumulate Unit) that will multiply the 2 input operands and add
the result to a register that has stored all previous results. The
figure 1 shows the simplest way to implement the MAC.
2.3 BUS ARCHITECTURES
Typically a GPP would have VonNeuman Architecture while a DSP would have Harvard Architecture.
VonNeuman architecture has a single data bus and an address bus and same memory where the data and
instructions are stored. Here instruction
fetching would cause a bottleneck. Refer
figure 2a. Harvard architecture separates
the data and address memories and so the
busses to access them are different too.
This allows instructions and data to be
processed separately and concurrently for
improved throughput and thus performance.
Refer figure 2b.