04-04-2012, 01:38 PM
REAL TIME CLOCK
[attachment=19453]
AIM:
Design a real time clock (2 digits,7 segments LED display each for Hours, Minutes and seconds) and demonstrate its working on the FPGA board.
APPARATUS REQUIRED:
• XILLINX ISE 9.2i software
• PC with Windows-XP
• FPGA board (SPARTAN-3E kit)
ALGORITHM:
• Create a verilog file.
• Assign port names.
• Write verilog program.
• Check syntax.
• Create UCF file.
• Assign package pin.
• Connect the Spartan 3E kit using JTag port and configure the device.
• Check on the shift and select program to download the program to FPGA.
• After the program is downloaded check the output using switches and LED.
PROGRAM:
[b]
[b]RESULT: [/b] [/b]
Thus the real time clock is designed and demonstrated its working on the FPGA board.
[attachment=19453]
AIM:
Design a real time clock (2 digits,7 segments LED display each for Hours, Minutes and seconds) and demonstrate its working on the FPGA board.
APPARATUS REQUIRED:
• XILLINX ISE 9.2i software
• PC with Windows-XP
• FPGA board (SPARTAN-3E kit)
ALGORITHM:
• Create a verilog file.
• Assign port names.
• Write verilog program.
• Check syntax.
• Create UCF file.
• Assign package pin.
• Connect the Spartan 3E kit using JTag port and configure the device.
• Check on the shift and select program to download the program to FPGA.
• After the program is downloaded check the output using switches and LED.
PROGRAM:
Code:
module timer(clk, rst, mode, set, sl, atoh);
input clk; // System Clock
input rst; // Reset(micro switch)
input [1:0]mode; // Mode Selection (switch 1 & switch 2)
input [7:0]set; // Set Value(switch 4 to switch 11)
output [5:0]sl; // Segment Selection
output [7:0]atoh; // Segment Display Control Data
reg[5:0] sl;
reg[7:0] atoh;
reg[26:0]sig2;
reg[19:1]sig3;
reg[7:0] ssdigit1;
reg[7:0] ssdigit2;
reg[7:0] ssdigit3;
reg[7:0] ssdigit4;
reg[7:0] ssdigit5;
reg[7:0] ssdigit6;
reg[3:0] digit1;
reg[3:0] digit2;
reg[3:0] digit3;
reg[3:0] digit4;
reg[3:0] digit5;
reg[3:0] digit6;
always @ (posedge clk or negedge rst)
begin
if (rst == 1'b0) begin
sig2 = 0;
sig3 = 0;
digit1 = 0;
digit2 = 0;
digit3 = 0;
digit4 = 0;
digit5 = 0;
digit6 = 0;
end
else begin
if (mode == 2'b00) begin // Hours
if (set[7:4] <= 4'b0001) begin
digit1 = set[7:4];
if (set[3:0] <= 4'b1001)
digit2 = set[3:0];
else
digit2 = 0;
end
else if (set[7:4] == 4'b0010) begin
if (set[3:0] <= 4'b0011) begin
digit1 = set[7:4];
digit2 = set[3:0];
end
else begin
digit1 = 0;
digit2 = 0;
end
end
else begin
digit1 = 0;
digit2 = 0;
end
end
else if (mode == 2'b01) begin // Minutes
if (set[7:4] <= 4'b0101) begin
digit3 = set[7:4];
if (set[3:0] <= 4'b1001)
digit4 = set[3:0];
else
digit4 = 0;
end
else begin
digit3 = 0;
digit4 = 0;
end
end
else if (mode == 2'b10) begin // Seconds
if (set[7:4] <= 4'b0101) begin
digit5 = set[7:4];
if (set[3:0] <= 4'b1001)
digit6 = set[3:0];
else
digit6 = 0;
end
else begin
digit5 = 0;
digit6 = 0;
end
end
else begin
sig2 = sig2 + 1;
case (sig2[24:23]) //RTC Function
2'b00 : begin
digit6 = digit6 + 1;
if (digit6 > 4'b1001) begin
digit6 = 4'b0000;
digit5 = digit5 + 1;
if (digit5 > 4'b0101) begin
digit5 = 4'b0000;
digit4 = digit4 + 1;
if (digit4 > 4'b1001) begin
digit4 = 4'b0000;
digit3 = digit3 + 1;
if (digit3 > 4'b0101) begin
digit3 = 4'b0000;
digit2 = digit2 + 1;
if (digit2 > 4'b1001) begin
digit2 = 4'b0000;
digit1 = digit1 + 1;
end
if ((digit1 >= 4'b0010) & (digit2 >= 4'b0100)) begin
digit1 = 4'b0000;
digit2 = 4'b0000;
end
end
end
end
end
sig2[24:23] = 2'b01;
end
2'b11 : begin
if (sig2[22:19] == 4'b1001)
sig2 = 0;
end
default : begin
end
endcase
end
// Display Settings
sig3 = sig3 + 1;
case (sig3[17:15])
3'b000 : begin
sl = 6'b111110;
case (digit1)
4'b0000 : ssdigit1 = 8'b00111111;
4'b0001 : ssdigit1 = 8'b00000110;
4'b0010 : ssdigit1 = 8'b01011011;
default : ssdigit1 = 8'b00000000;
endcase
atoh = ssdigit1;
end
3'b001 : begin
sl = 6'b111101;
case (digit2)
4'b0000 : ssdigit2 = 8'b00111111;
4'b0001 : ssdigit2 = 8'b00000110;
4'b0010 : ssdigit2 = 8'b01011011;
4'b0011 : ssdigit2 = 8'b01001111;
4'b0100 : ssdigit2 = 8'b01100110;
4'b0101 : ssdigit2 = 8'b01101101;
4'b0110 : ssdigit2 = 8'b01111101;
4'b0111 : ssdigit2 = 8'b00000111;
4'b1000 : ssdigit2 = 8'b01111111;
4'b1001 : ssdigit2 = 8'b01101111;
default : ssdigit2 = 8'b00000000;
endcase
atoh = ssdigit2;
end
3'b011 : begin
sl = 6'b111011;
case (digit3)
4'b0000 : ssdigit3 = 8'b00111111;
4'b0001 : ssdigit3 = 8'b00000110;
4'b0010 : ssdigit3 = 8'b01011011;
4'b0011 : ssdigit3 = 8'b01001111;
4'b0100 : ssdigit3 = 8'b01100110;
4'b0101 : ssdigit3 = 8'b01101101;
default : ssdigit3 = 8'b00000000;
endcase
atoh = ssdigit3;
end
3'b100 : begin
sl = 6'b110111;
case (digit4)
4'b0000 : ssdigit4 = 8'b00111111;
4'b0001 : ssdigit4 = 8'b00000110;
4'b0010 : ssdigit4 = 8'b01011010;
4'b0011 : ssdigit4 = 8'b01001111;
4'b0100 : ssdigit4 = 8'b01100110;
4'b0101 : ssdigit4 = 8'b01101101;
4'b0110 : ssdigit4 = 8'b01111101;
4'b0111 : ssdigit4 = 8'b00000111;
4'b1000 : ssdigit4 = 8'b01111111;
4'b1001 : ssdigit4 = 8'b01101111;
default : ssdigit4 = 8'b00000000;
endcase
atoh = ssdigit4;
end
3'b110 : begin
sl = 6'b101111;
case (digit5)
4'b0000 : ssdigit5 = 8'b00111111;
4'b0001 : ssdigit5 = 8'b00000110;
4'b0010 : ssdigit5 = 8'b01011011;
4'b0011 : ssdigit5 = 8'b01001111;
4'b0100 : ssdigit5 = 8'b01100110;
4'b0101 : ssdigit5 = 8'b01101101;
default : ssdigit5 = 8'b00000000;
endcase
atoh = ssdigit5;
end
3'b111 : begin
sl = 6'b011111;
case (digit6)
4'b0000 : ssdigit6 = 8'b00111111;
4'b0001 : ssdigit6 = 8'b00000110;
4'b0010 : ssdigit6 = 8'b01011011;
4'b0011 : ssdigit6 = 8'b01001111;
4'b0100 : ssdigit6 = 8'b01100110;
4'b0101 : ssdigit6 = 8'b01101101;
4'b0110 : ssdigit6 = 8'b01111101;
4'b0111 : ssdigit6 = 8'b00000111;
4'b1000 : ssdigit6 = 8'b01111111;
4'b1001 : ssdigit6 = 8'b01101111;
default : ssdigit6 = 8'b00000000;
endcase
atoh = ssdigit6;
end
endcase
end
end
endmodule[b]RESULT: [/b] [/b]
Thus the real time clock is designed and demonstrated its working on the FPGA board.