04-04-2012, 01:47 PM
STUDY OF SCHEMATIC ENTRY
[attachment=19455]
AIM:
To study the development tools of FPGA for schematic entry of equality detector.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new schematic source file.
• Draw the circuit using logic gates.
• Give port name
• Create test bench waveform & input.
• Simulate using ISE simulation or synthesis using XST Simulation.
THEORY:
• Schematic entry is given using ISE truth table is generated for required functionality.
• The equations are solved and get the gates to implement the design.
• Instead of using or writing codes, here we have circuit logic diagram and get output either using simulator or
synthesizer.
RESULT:
Thus the development tools of FPGA for schematic entry of equality detector are studied.
[attachment=19455]
AIM:
To study the development tools of FPGA for schematic entry of equality detector.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new schematic source file.
• Draw the circuit using logic gates.
• Give port name
• Create test bench waveform & input.
• Simulate using ISE simulation or synthesis using XST Simulation.
THEORY:
• Schematic entry is given using ISE truth table is generated for required functionality.
• The equations are solved and get the gates to implement the design.
• Instead of using or writing codes, here we have circuit logic diagram and get output either using simulator or
synthesizer.
RESULT:
Thus the development tools of FPGA for schematic entry of equality detector are studied.