04-04-2012, 01:55 PM
STUDY OF SIMULATION TOOLS
[attachment=19457]
AIM:
To Study Simulation Tools Using priority encoder&decoder.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a verilog file
• Assign port names
• Write verilog program
• Check syntax
• Create a test bench waveform and give input
• Simulate the parallel adder using ISE simulator
THEORY:
The simulator environment must maintain information about various design units involved in simulation such as location libraries . If the Verilog HDL analyzer returns errors relating to the absence of key libraries, it is mostly likely a result of the lack of definition of Physical location of the Logical libraries. After finishing the program we need to generate a test case and provide stimulus to the model to determine if the model is indeed operating correctly. Generally most simulators will provide for ways in which to specify a waveform on an input port of the entity being loaded. There will also be facilities for forcing signals to a certain values. Signal initialization, especially on input ports, is a necessary prelude to simulation
PROGRAM:
DECODER:
RESULT:
Thus the simulation tools were studied using priority encoder and decoder.
[attachment=19457]
AIM:
To Study Simulation Tools Using priority encoder&decoder.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a verilog file
• Assign port names
• Write verilog program
• Check syntax
• Create a test bench waveform and give input
• Simulate the parallel adder using ISE simulator
THEORY:
The simulator environment must maintain information about various design units involved in simulation such as location libraries . If the Verilog HDL analyzer returns errors relating to the absence of key libraries, it is mostly likely a result of the lack of definition of Physical location of the Logical libraries. After finishing the program we need to generate a test case and provide stimulus to the model to determine if the model is indeed operating correctly. Generally most simulators will provide for ways in which to specify a waveform on an input port of the entity being loaded. There will also be facilities for forcing signals to a certain values. Signal initialization, especially on input ports, is a necessary prelude to simulation
PROGRAM:
DECODER:
Code:
module decoder(a, b, e, d0, d1, d2, d3);
input a;
input b;
input e;
output d0;
output d1;
output d2;
output d3;
assign d0=~(~a&~e&~b);
assign d1=~(~a&~e&b);
assign d2=~(a&~e&~b);
assign d3=~(a&~e&b);
endmodule
[b]
ENCODER:[/b]
module encoder(d0, d1, d2, d3, e0, e1, e2);
input d0;
input d1;
input d2;
input d3;
output e0;
output e1;
output e2;
assign e0=(d3/(~d2&d1));
assign e1=(d3/d2);
assign e2=(d3/d2/(d1/d0));
endmoduleRESULT:
Thus the simulation tools were studied using priority encoder and decoder.