04-04-2012, 02:26 PM
STUDY OF SYNTHESIS TOOLS
[attachment=19458]
AIM:
To study the synthesis tools using half adder and full adder.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new verilog file
• Assign port names
• Write verilog program
• Check syntax
• Synthesis the program to view RTL schematic and technology schematic
PROGRAM:
//FOR HALF ADDER:
THEORY:
Synthesis is an automatic method of converting a higher level abstraction to a lower level abstraction. The synthesis tool covert register transfer level (RTL) description
to gate level netlists. These gate level netlists consists of interconnected gate level macro cells. These gate level netlists currently can be optimized for area, speed etc.,
The analyzed design is synthesized to library of components, typically gates, latches, or flipflops. Hierarchical designs are synthesized in bottom up fasion that is lower level components
are synthesized before higher level components. Once the design is synthesized we have a gate level netlist. This gate level netlist can be simulated. Delay for the individual components are available as part of the description of the component libraries. Timing accurate simulation is not possible at this point because the actual timing characteristics are determined by the physical placement of the design with the FPGA chip. However, the functional simulation that is possible at this point is quite a bit more accurate than simulation based on user specified delays.
RESULT:
Thus the synthesis tools using half adder and full adder is studied.
[attachment=19458]
AIM:
To study the synthesis tools using half adder and full adder.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new verilog file
• Assign port names
• Write verilog program
• Check syntax
• Synthesis the program to view RTL schematic and technology schematic
PROGRAM:
//FOR HALF ADDER:
Code:
module halfadder(a, b, s, c);
input a;
input b;
output s;
output c;
assign s = a ^ b; // sum = a xor b
assign c = a & b; // carry = a and b
endmodule
[b]
//FOR FULL ADDER: [/b]
module fulladder(a,b,c,sum,carry);
input a;
input b;
input c;
output sum;
output carry;
assign sum=a^b^c;
assign carry=((a^b)&c)(a&b));
endmoduleTHEORY:
Synthesis is an automatic method of converting a higher level abstraction to a lower level abstraction. The synthesis tool covert register transfer level (RTL) description
to gate level netlists. These gate level netlists consists of interconnected gate level macro cells. These gate level netlists currently can be optimized for area, speed etc.,
The analyzed design is synthesized to library of components, typically gates, latches, or flipflops. Hierarchical designs are synthesized in bottom up fasion that is lower level components
are synthesized before higher level components. Once the design is synthesized we have a gate level netlist. This gate level netlist can be simulated. Delay for the individual components are available as part of the description of the component libraries. Timing accurate simulation is not possible at this point because the actual timing characteristics are determined by the physical placement of the design with the FPGA chip. However, the functional simulation that is possible at this point is quite a bit more accurate than simulation based on user specified delays.
RESULT:
Thus the synthesis tools using half adder and full adder is studied.