02-05-2012, 05:00 PM
Developing new low-power chip-design methods for mobile applications
Consumers expect each new generation of mobile electronic devices to perform even better than the last. Whether it is a mobile phone, MP3 player, personal digital assistant (PDA) or laptop computer, a new device has to be physically smaller, yet offer more power, more user-friendly applications and longer battery life.
Such expectations place great pressure on the electronic system designers. More powerful processors usually generate more heat, and do not tend to be good for battery life. And, as the physical envelope gets smaller, problems of power leakage and overall system temperature become ever greater.
Now that system designers are already work¬ing at submicron levels, they have estimated that with the present rate of miniaturisation, system temperatures could rise over the next decade from the equivalent of a warm dinner plate to that of the surface of the sun! They need to find innovative solutions therefore if static and dynamic power consumption is to be controlled and the heat penalty does result in total meltdown.
Low-power expertise
The MEDEA+ 2A708 LoMoSA+ project therefore set out to develop new and innovative solu¬tions to low-power design, especially for mobile applications. With low-power methods seen as critical to the success of future mobile devices, the project partners aimed to develop new, Europe-wide low-power expertise for mobile and multimedia applications.
A key objective was to reduce overall system power consumption for both active and stand¬by power. To meet this, participants worked in five main areas: defining platform architec¬tures, examining hardware platform components, checking the compatibility of hardware-dependent software (HdS) and real-time oper¬ating systems, looking at design methodologies and developing suitable mobile and multimedia demonstrators.
As well as investigating low-power solutions for bus-controlled system-on-chip (SoC) designs, the work of the consortium, which included chipmakers, systems manufacturers, research laboratories and a silicon design house, embraced the impact on power, scalability and performance of future multiprocessor SoC infrastructures that make use of novel on-chip communications solutions.
LoMoSA+ developed technological innovations in several areas, including:
• A new integrated low-power platform archi¬tecture;
• Power-aware design methodologies;
• New reusable, power-efficient digital and analogue hardware components to form the building blocks of the platform;
• Development of HdS technology for applica¬ tion-driven design of network-on-chip (NoC) architectures – HdS is a key enabler of 65 nm technology platforms for European SoC applications.
Fast-changing environment
Despite a series of changes in status among a number of the partners, including impor¬tant reorganisations within NXP, Thomson and STMicroelectronics and the entry of the newly formed STMicroelectronics-NXP Wireless joint venture that became ST Ericsson in 2009, most of the project mile¬stones and deliverables were realised.
In particular, the partners managed to achieve a 30 to 40% overall reduction in power con-sumption, an advance particularly relevant for mobile phone components, as well as sig-nificant reductions in backlight consumption for LCD screens. In certain application areas, they were able to meet or even extend the original 70% power-reduction target.
Work in the project has enabled one partner, STMicroelectronics, to promote and demon¬strate the feasibility of power-aware multi¬processors and associated NoC solutions within the company, with the goal of embed¬ding such solutions into the next generation of chips.
Another partner, Thomson, has been able to develop two SoC designs for use in the video/ audio coding/decoding domain. One of these designs is intended for set-top box products. The other, for professional broadcast equip¬ment, has underpinned the development of a number of professional coders, decoders and transcoders, some of which are already on the market.
Consumers expect each new generation of mobile electronic devices to perform even better than the last. Whether it is a mobile phone, MP3 player, personal digital assistant (PDA) or laptop computer, a new device has to be physically smaller, yet offer more power, more user-friendly applications and longer battery life.
Such expectations place great pressure on the electronic system designers. More powerful processors usually generate more heat, and do not tend to be good for battery life. And, as the physical envelope gets smaller, problems of power leakage and overall system temperature become ever greater.
Now that system designers are already work¬ing at submicron levels, they have estimated that with the present rate of miniaturisation, system temperatures could rise over the next decade from the equivalent of a warm dinner plate to that of the surface of the sun! They need to find innovative solutions therefore if static and dynamic power consumption is to be controlled and the heat penalty does result in total meltdown.
Low-power expertise
The MEDEA+ 2A708 LoMoSA+ project therefore set out to develop new and innovative solu¬tions to low-power design, especially for mobile applications. With low-power methods seen as critical to the success of future mobile devices, the project partners aimed to develop new, Europe-wide low-power expertise for mobile and multimedia applications.
A key objective was to reduce overall system power consumption for both active and stand¬by power. To meet this, participants worked in five main areas: defining platform architec¬tures, examining hardware platform components, checking the compatibility of hardware-dependent software (HdS) and real-time oper¬ating systems, looking at design methodologies and developing suitable mobile and multimedia demonstrators.
As well as investigating low-power solutions for bus-controlled system-on-chip (SoC) designs, the work of the consortium, which included chipmakers, systems manufacturers, research laboratories and a silicon design house, embraced the impact on power, scalability and performance of future multiprocessor SoC infrastructures that make use of novel on-chip communications solutions.
LoMoSA+ developed technological innovations in several areas, including:
• A new integrated low-power platform archi¬tecture;
• Power-aware design methodologies;
• New reusable, power-efficient digital and analogue hardware components to form the building blocks of the platform;
• Development of HdS technology for applica¬ tion-driven design of network-on-chip (NoC) architectures – HdS is a key enabler of 65 nm technology platforms for European SoC applications.
Fast-changing environment
Despite a series of changes in status among a number of the partners, including impor¬tant reorganisations within NXP, Thomson and STMicroelectronics and the entry of the newly formed STMicroelectronics-NXP Wireless joint venture that became ST Ericsson in 2009, most of the project mile¬stones and deliverables were realised.
In particular, the partners managed to achieve a 30 to 40% overall reduction in power con-sumption, an advance particularly relevant for mobile phone components, as well as sig-nificant reductions in backlight consumption for LCD screens. In certain application areas, they were able to meet or even extend the original 70% power-reduction target.
Work in the project has enabled one partner, STMicroelectronics, to promote and demon¬strate the feasibility of power-aware multi¬processors and associated NoC solutions within the company, with the goal of embed¬ding such solutions into the next generation of chips.
Another partner, Thomson, has been able to develop two SoC designs for use in the video/ audio coding/decoding domain. One of these designs is intended for set-top box products. The other, for professional broadcast equip¬ment, has underpinned the development of a number of professional coders, decoders and transcoders, some of which are already on the market.