07-05-2012, 02:48 PM
interrupt controller
[attachment=21474]
INTERRUPT CONTROLLER
The interrupt controller is a device commonly found in computer system (both sing and multi processor), which deals with the interrupt generated by the peripherals and processors, handle the interrupt priorities and delegates the execution of the processors.
Interrupt controller architecture
The high level block diagram of the interrupt architecture is shown in the Fig.1.8. It is composed by two main components: the first one is the (OPB interface) block which interfaces the core with the main bus of the system, the second one (int core) implements the true logic of the controller.
Controller logic
The second component Int Core, implement the core logic of the controller. As the picture shows, it is composed by three subcomponents, each one with specific processor:
The register block provides a useful support for all the main facilities of our Interrupt controller. It allows handling of the Interrupt priorities; decide ding which Interrupt can be handled and managing of the interrupt acknowledge signals. To allow each processor to respond only to the interrupt generated by a specific ips (booking) and to allow broadcasting of interrupts to all the processors in the system
SOFTWARE LAYER
The software layer is composed by a driver and a generic interrupt handler. The driver exposes the Interrupt Controller features to the processors. It contains three main functions to implement booking, broadcasting, and inter-processor communication. The next section discusses the detailed behavior of our architecture when dealing with these features. The generic interrupt handler is called DeviceInterruptHandler and executes whenever a processor receives an interrupt request. This routine chooses which is the interrupt to handle by reading the Interrupt Controller registers, acknowledges the Interrupt Controller and launches the specific interrupt handler to manage the event. If it is an interrupt from a peripheral, the handler included in the peripheral driver is executed.
[attachment=21474]
INTERRUPT CONTROLLER
The interrupt controller is a device commonly found in computer system (both sing and multi processor), which deals with the interrupt generated by the peripherals and processors, handle the interrupt priorities and delegates the execution of the processors.
Interrupt controller architecture
The high level block diagram of the interrupt architecture is shown in the Fig.1.8. It is composed by two main components: the first one is the (OPB interface) block which interfaces the core with the main bus of the system, the second one (int core) implements the true logic of the controller.
Controller logic
The second component Int Core, implement the core logic of the controller. As the picture shows, it is composed by three subcomponents, each one with specific processor:
The register block provides a useful support for all the main facilities of our Interrupt controller. It allows handling of the Interrupt priorities; decide ding which Interrupt can be handled and managing of the interrupt acknowledge signals. To allow each processor to respond only to the interrupt generated by a specific ips (booking) and to allow broadcasting of interrupts to all the processors in the system
SOFTWARE LAYER
The software layer is composed by a driver and a generic interrupt handler. The driver exposes the Interrupt Controller features to the processors. It contains three main functions to implement booking, broadcasting, and inter-processor communication. The next section discusses the detailed behavior of our architecture when dealing with these features. The generic interrupt handler is called DeviceInterruptHandler and executes whenever a processor receives an interrupt request. This routine chooses which is the interrupt to handle by reading the Interrupt Controller registers, acknowledges the Interrupt Controller and launches the specific interrupt handler to manage the event. If it is an interrupt from a peripheral, the handler included in the peripheral driver is executed.