07-05-2012, 04:16 PM
MICROCONTROLLER 89S51
[attachment=21493]
INTRODUCTION:
The 8051 family of microcontrollers is based on architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on PC. The basic architecture consists of the following features:
One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second .inverting this will provide the amount of time taken by each instruction cycle. Features of a microcontroller is given as follows:
An eight bit ALU
32 discrete I/O pins (4 groups of 8) which can be individually accessed
Two 16 bit timer /counters
Full duplex UART
6 interrupt sources with 2 priority levels
28 bytes of on board RAM
Separate 64K byte address spaces for DATA and CODE memory
MEMORY ORGANIZATION:
The 8051 architecture provides the user with three physically distinct memory spaces which can be seen in figure 3.1.Each memory space consists of contiguous addresses from 0 to maximum
size, in bytes, of the memory space .Address overlaps are resolved by utilizing theseinstructions which refer specifically to a given address space. The three memory spaces function as described below.
THE CODE SPACE:
The first memory space is the CODE segment in which the executable program resides. This segment can be upto 64K (since it is addressed by 16 address lines). The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM. However, this does not mean that the CODE segment must be implemented using an EPROM. Many embedded systems these days are using EEPROM which allows the memory to be overwritten either by the 8051 itself or by an external device. This makes upgrade to the product easy to do since new software can be downloaded into the EEPROM rather than having to disassemble it and install a new EPROM.
THE DATA SPACE:
The second memory space is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the DATA segment. The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than access to the XDATA segment because memory is directly rather than via a memory pointer such as DPTR which must first be initialized. Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment.
Variables stored in the DATA segment can also be accessed indirectly via R0 or R1.The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles depending on the source/destination data byte.
PROCESSOR STATUS:
Processor status is kept in a bit addressable SFR called PSW(Processor Status Word).This register contains the carry bit, an auxiliary bit which is used with BCD operations, the Accumulator parity flag and overflow flag, two general purpose flags, and two bits which select the register bank to use as the default. As mentioned before, the register bank selection bits make a two bit number from 0 to 3 which indicate the bank to be used. Bank 0 begins at the base of the DATA segment (address 00H), bank 1 begins at 08H, bank 2 begins at address 10H and bank 3 at address 18H.Any of these memory locations are always available for direct and indirect memory accesses via their addresses regardless of the register bank selection.
POWER CONTROL:
The CHMOS versions of the 8051 feature two power saving modes that can be activated by software: idle mode and power down mode. These modes are accessed via the PCON (Power Control). The idle mode is activated by setting the IDLE bit high. The idle mode causes all program execution to stop. Internal RAM contents are preserved and the oscillator continues to run but is
blocked from the CPU. The timers and the UART continue to function as normal. Idle mode is terminated by the activation of any interrupt. Upon completion of the interrupt service routine, execution will continue from the instruction following the instruction which set the IDLE bit.
INTERRUPTS OF 8051:
The basic 8051 supports six interrupt sources: two external interrupts, two timer/counter interrupts, and a serial byte in/out interrupt. These interrupt sources force the processor to vector to one of five locations in the lowest part of the CODE address space (serial input and serial output interrupts share the same vector ). The interrupt service routine must either reside there or be branched from there.
[attachment=21493]
INTRODUCTION:
The 8051 family of microcontrollers is based on architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on PC. The basic architecture consists of the following features:
One 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second .inverting this will provide the amount of time taken by each instruction cycle. Features of a microcontroller is given as follows:
An eight bit ALU
32 discrete I/O pins (4 groups of 8) which can be individually accessed
Two 16 bit timer /counters
Full duplex UART
6 interrupt sources with 2 priority levels
28 bytes of on board RAM
Separate 64K byte address spaces for DATA and CODE memory
MEMORY ORGANIZATION:
The 8051 architecture provides the user with three physically distinct memory spaces which can be seen in figure 3.1.Each memory space consists of contiguous addresses from 0 to maximum
size, in bytes, of the memory space .Address overlaps are resolved by utilizing theseinstructions which refer specifically to a given address space. The three memory spaces function as described below.
THE CODE SPACE:
The first memory space is the CODE segment in which the executable program resides. This segment can be upto 64K (since it is addressed by 16 address lines). The processor treats this segment as read only and will generate signals appropriate to access a memory device such as an EPROM. However, this does not mean that the CODE segment must be implemented using an EPROM. Many embedded systems these days are using EEPROM which allows the memory to be overwritten either by the 8051 itself or by an external device. This makes upgrade to the product easy to do since new software can be downloaded into the EEPROM rather than having to disassemble it and install a new EPROM.
THE DATA SPACE:
The second memory space is the 128 bytes of internal RAM on the 8051, or the first 128 bytes of internal RAM on the 8052. This segment is typically referred to as the DATA segment. The RAM locations in this segment are accessed in one or two cycles depending on the instruction. This access time is much quicker than access to the XDATA segment because memory is directly rather than via a memory pointer such as DPTR which must first be initialized. Therefore, frequently used variables and temporary scratch variables are usually assigned to the DATA segment.
Variables stored in the DATA segment can also be accessed indirectly via R0 or R1.The register being used as the memory pointer must contain the address of the byte to be retrieved or altered. These instructions can take one or two processor cycles depending on the source/destination data byte.
PROCESSOR STATUS:
Processor status is kept in a bit addressable SFR called PSW(Processor Status Word).This register contains the carry bit, an auxiliary bit which is used with BCD operations, the Accumulator parity flag and overflow flag, two general purpose flags, and two bits which select the register bank to use as the default. As mentioned before, the register bank selection bits make a two bit number from 0 to 3 which indicate the bank to be used. Bank 0 begins at the base of the DATA segment (address 00H), bank 1 begins at 08H, bank 2 begins at address 10H and bank 3 at address 18H.Any of these memory locations are always available for direct and indirect memory accesses via their addresses regardless of the register bank selection.
POWER CONTROL:
The CHMOS versions of the 8051 feature two power saving modes that can be activated by software: idle mode and power down mode. These modes are accessed via the PCON (Power Control). The idle mode is activated by setting the IDLE bit high. The idle mode causes all program execution to stop. Internal RAM contents are preserved and the oscillator continues to run but is
blocked from the CPU. The timers and the UART continue to function as normal. Idle mode is terminated by the activation of any interrupt. Upon completion of the interrupt service routine, execution will continue from the instruction following the instruction which set the IDLE bit.
INTERRUPTS OF 8051:
The basic 8051 supports six interrupt sources: two external interrupts, two timer/counter interrupts, and a serial byte in/out interrupt. These interrupt sources force the processor to vector to one of five locations in the lowest part of the CODE address space (serial input and serial output interrupts share the same vector ). The interrupt service routine must either reside there or be branched from there.