11-05-2012, 11:08 AM
VLSI IMPLEMENTATION ON EXTENDED SERVICE ORIENTED ARCHITECTURE FOR WIRELESS SENSOR NETWORK
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INTRODUCTION
WIRELESS SENSOR NETWORK
Represent one of the most challenging areas in today’s electronic
industry . These networks are expected to be autonomous, low-power demanding, context aware, and flexible. A final application may have hundreds or thousands of sensor nodes spread out in an environment, making the deployment and the support of WSNs a complex task. Although the integration technologies are clearly tending to smart sensor, there is still an increasing variety of sensors. The interfaces and data processing required for sensors control are very different not only from one sensor to another, but also from one application to another. In such context, the use of identical nodes or a reduced set of nodes that are further adapted and/or customized would simplify the deployment process and reduce the product cost.
Classic design approaches for WSNs node rely on the use of a microcontroller ( C). However, processing and functionality needs are continuously increasing due to new application requirements and this includes WSNs applications. This, added to the constantly increasing pressure for reducing time-to-market, has led to new design alternatives, such as reconfigurable hardware (HW). Reconfigurable systems have been studied in the last years as an alternative for both: Application-Specific Integrated Circuits (ASICs) and General Purpose Processors (GPPs). GPPs, for instance, suffer an imbalance between IO (device Input-Outputs)
and processing. Differently, FPGAs provide not only a large amount of IOs, but also high processing due to the offered inherited of parallelism and pipelining. Furthermore, reconfigurable systems provide high flexibility as they can be updated after system deployment and also permit time to market
reduction, since the proper prototype can be the final device. As a result, reconfigurable devices are constantly gaining market share and extending their industry application domains and research interest. For instance, the work presented in focuses on the application of FPGAs in industry control systems. Even more, now, it is possible to implement neural networks and fuzzy control solutions on FPGAs and also, reconfigurable computing has been widely explored in accelerating applications, like calculations related to molecular dynamics in This paper is focused on the use of reconfigurable systems in
WSNs. Several research groups have already exploited the benefits of HW parallelism by designing ad-hoc reconfigurable devices prepared to be adapted to a set of prerecorded applications, like in and. The flexibility achieved with this approach is higher compared to ASIC-based solutions, but not as high as with small grain reconfigurable devices, like FPGAs. In addition to this, custom solutions are more restricted as they require specific Computer Aided Design (CAD) tools. Differently, this paper exploits industry available reconfigurable devices looking for high adaptability and flexibility through the use of the partial runtime reconfiguration technique, while taking advantage of the vendor provided CAD tools. In particular, this paper aims to explore and evaluate the use of partial runtime reconfiguration in WSNs, topic that has not been explored in the state-of-the-art. Runtime reconfiguration is an advanced topic within the reconfigurable computing area, where changes into the FPGA configuration are done at runtime, while the device I/Os and remaining logic is kept active. This powerful feature (only included in Xilinx and Atmel FPGAs) permits not only to perform HW updates at runtime and at anytime, but also to save memory space and programming time compared to full FPGA reconfiguration. Partial reconfiguration has already been exploited in the automotive industry and in shape-adaptive video applications, where different reconfiguration strategies are studied. Runtime reconfiguration will be tested in a HW platform for WSNs developed at CEI, called Cookies and first presented in. This platform is overviewed in the paper, along with an outline of the WSNs state-of-the-art, in order to highlight its distinguishing characteristics.
VLSI OVERVIEW
HISTORICAL PERSPECTIVE:
The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the advent of VLSI. The number of applications of integrated circuits in high-performance computing, telecommunications and consumer electronics has been raising steadily and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field. The current leading-edge technologies such as low bit-rate video and cellular communications already provide the end users a certain amount of processing power and portability. This trend is expected to be continued with very important implications of VLSI and systems design.
As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these function in the small system /package is also increasing .The level of integration as measured by the number of logic gates in a monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Shows the evolution of logic complexity in integrated circuits over the last three decades, and marks the milestone of each era. Here, the numbers for circuit complexity should be interpreted only as representative examples to show the order of magnitude. A logic block can contain ten to hundred transistors depending upon the function.
The important message here is that the logic complexity per chip has been increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides:
• Less area / volume and therefore compactness.
• Less power consumption.
• Less testing requirements at system level.
• Higher reliability, mainly due to improved on-chip
Interconnects.
• Higher speed, due to significantly reduced
interconnection length.
• Significant cost savings.
Therefore, the current trend of integration will also continue in the foreseeable future.
A minimum size of 0.25 microns was readily achievable by the year 1995.As a direct result of this, the integration density has also exceeded previous expectations-the first 64 Ambit DRAM and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994,pushing the envelope of the integration density.
VHDL –An Overview
INTRODUCTION:
VHDL is a hardware description language. The word ‘hardware’ however is used in a wide variety of contexts, which range from complete systems like personal computers on one side to the small logical on their internal integrated circuits on the other side.
HISTORY OF VHDL:
The requirements for the language were first generated in 1981 under the VHSIC program. In this program , a number of U.S companies were involved in designing VHSIC chips for the Department of Defense (DoD). At that time most of the companies were using different languages to describe and develop their integrated circuits. As a result, a different vendors could not effectively exchange designs with one another. A team of three companies IMB, Texas Instruments, and Intermetrics were First awarded the contract by the DoD to develop a version of the language in 1983.
version 7.2 of VHDL was developed and released to the public in 1985. After the release of version 7.2, there was an increasing need to make the language an industry-widestandard. Consequently, the language was transferred to the IEEE for standardization in 1987.
[attachment=21834]
INTRODUCTION
WIRELESS SENSOR NETWORK
Represent one of the most challenging areas in today’s electronic
industry . These networks are expected to be autonomous, low-power demanding, context aware, and flexible. A final application may have hundreds or thousands of sensor nodes spread out in an environment, making the deployment and the support of WSNs a complex task. Although the integration technologies are clearly tending to smart sensor, there is still an increasing variety of sensors. The interfaces and data processing required for sensors control are very different not only from one sensor to another, but also from one application to another. In such context, the use of identical nodes or a reduced set of nodes that are further adapted and/or customized would simplify the deployment process and reduce the product cost.
Classic design approaches for WSNs node rely on the use of a microcontroller ( C). However, processing and functionality needs are continuously increasing due to new application requirements and this includes WSNs applications. This, added to the constantly increasing pressure for reducing time-to-market, has led to new design alternatives, such as reconfigurable hardware (HW). Reconfigurable systems have been studied in the last years as an alternative for both: Application-Specific Integrated Circuits (ASICs) and General Purpose Processors (GPPs). GPPs, for instance, suffer an imbalance between IO (device Input-Outputs)
and processing. Differently, FPGAs provide not only a large amount of IOs, but also high processing due to the offered inherited of parallelism and pipelining. Furthermore, reconfigurable systems provide high flexibility as they can be updated after system deployment and also permit time to market
reduction, since the proper prototype can be the final device. As a result, reconfigurable devices are constantly gaining market share and extending their industry application domains and research interest. For instance, the work presented in focuses on the application of FPGAs in industry control systems. Even more, now, it is possible to implement neural networks and fuzzy control solutions on FPGAs and also, reconfigurable computing has been widely explored in accelerating applications, like calculations related to molecular dynamics in This paper is focused on the use of reconfigurable systems in
WSNs. Several research groups have already exploited the benefits of HW parallelism by designing ad-hoc reconfigurable devices prepared to be adapted to a set of prerecorded applications, like in and. The flexibility achieved with this approach is higher compared to ASIC-based solutions, but not as high as with small grain reconfigurable devices, like FPGAs. In addition to this, custom solutions are more restricted as they require specific Computer Aided Design (CAD) tools. Differently, this paper exploits industry available reconfigurable devices looking for high adaptability and flexibility through the use of the partial runtime reconfiguration technique, while taking advantage of the vendor provided CAD tools. In particular, this paper aims to explore and evaluate the use of partial runtime reconfiguration in WSNs, topic that has not been explored in the state-of-the-art. Runtime reconfiguration is an advanced topic within the reconfigurable computing area, where changes into the FPGA configuration are done at runtime, while the device I/Os and remaining logic is kept active. This powerful feature (only included in Xilinx and Atmel FPGAs) permits not only to perform HW updates at runtime and at anytime, but also to save memory space and programming time compared to full FPGA reconfiguration. Partial reconfiguration has already been exploited in the automotive industry and in shape-adaptive video applications, where different reconfiguration strategies are studied. Runtime reconfiguration will be tested in a HW platform for WSNs developed at CEI, called Cookies and first presented in. This platform is overviewed in the paper, along with an outline of the WSNs state-of-the-art, in order to highlight its distinguishing characteristics.
VLSI OVERVIEW
HISTORICAL PERSPECTIVE:
The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the advent of VLSI. The number of applications of integrated circuits in high-performance computing, telecommunications and consumer electronics has been raising steadily and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field. The current leading-edge technologies such as low bit-rate video and cellular communications already provide the end users a certain amount of processing power and portability. This trend is expected to be continued with very important implications of VLSI and systems design.
As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these function in the small system /package is also increasing .The level of integration as measured by the number of logic gates in a monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Shows the evolution of logic complexity in integrated circuits over the last three decades, and marks the milestone of each era. Here, the numbers for circuit complexity should be interpreted only as representative examples to show the order of magnitude. A logic block can contain ten to hundred transistors depending upon the function.
The important message here is that the logic complexity per chip has been increasing exponentially. The monolithic integration of a large number of functions on a single chip usually provides:
• Less area / volume and therefore compactness.
• Less power consumption.
• Less testing requirements at system level.
• Higher reliability, mainly due to improved on-chip
Interconnects.
• Higher speed, due to significantly reduced
interconnection length.
• Significant cost savings.
Therefore, the current trend of integration will also continue in the foreseeable future.
A minimum size of 0.25 microns was readily achievable by the year 1995.As a direct result of this, the integration density has also exceeded previous expectations-the first 64 Ambit DRAM and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994,pushing the envelope of the integration density.
VHDL –An Overview
INTRODUCTION:
VHDL is a hardware description language. The word ‘hardware’ however is used in a wide variety of contexts, which range from complete systems like personal computers on one side to the small logical on their internal integrated circuits on the other side.
HISTORY OF VHDL:
The requirements for the language were first generated in 1981 under the VHSIC program. In this program , a number of U.S companies were involved in designing VHSIC chips for the Department of Defense (DoD). At that time most of the companies were using different languages to describe and develop their integrated circuits. As a result, a different vendors could not effectively exchange designs with one another. A team of three companies IMB, Texas Instruments, and Intermetrics were First awarded the contract by the DoD to develop a version of the language in 1983.
version 7.2 of VHDL was developed and released to the public in 1985. After the release of version 7.2, there was an increasing need to make the language an industry-widestandard. Consequently, the language was transferred to the IEEE for standardization in 1987.