16-05-2012, 01:48 PM
hyper transport technology
Abstract
cc In older multi-drop bus architectures like PCI, the addition of hardware devices affects the overall electrical characteristics and bandwidth of the entire bus. Even with PCI-X1.0, the maximum supported clock speed of 133MHz must be reduced when more than one PCI-X device is attached. Hyper Transport technology uses a point-to-point link that is connected between two devices, enabling the overall speed of the link to transfer data much faster
the entire bus. Even with PCI-X1.0, the maximum supported clock speed of 133MHz must be reduced when more than one PCI-X de
Abstract
cc In older multi-drop bus architectures like PCI, the addition of hardware devices affects the overall electrical characteristics and bandwidth of the entire bus. Even with PCI-X1.0, the maximum supported clock speed of 133MHz must be reduced when more than one PCI-X device is attached. Hyper Transport technology uses a point-to-point link that is connected between two devices, enabling the overall speed of the link to transfer data much faster
the entire bus. Even with PCI-X1.0, the maximum supported clock speed of 133MHz must be reduced when more than one PCI-X de