21-05-2012, 01:00 PM
Image Compression on FPGA using DCT
[attachment=22555]
INTRODUCTION
large number of image data compression techniques areavailable, each one being adapted to a specific type of application, such as: compact disc, videoconference, videophone and multimedia systems. In all of these applications the transmission line bandwidth will determine
the compression standard to be used [1]. Among these, there is a compression technique based on a frequency transform called a Discrete Cosine Transform (DCT). This transform contains unique characteristics which allow for the creation of an efficient image compression; image and video compressors and decompressors are implemented in both
software and hardware. However, hardware implementations are especially important for the realization of highly parallel algorithms and can achieve much higher throughput than software solutions. The DCT transform was greatly enhanced by its implementation in VLSI circuits,
which are becoming increasingly faster. VLSI circuits are now capable of executing a DCT transform in real time. In this paper, we present the methodology to implement the DCT. The proposed system could be useful in many other applications that require image data compression. We describe in section II the general description of the codec image video system that required the data compression. The DCT hardware design implementations are subjects of section III. Section IV contains the implementation process of the DCT using FPGA and its experimental results. Finally, conclusion is given in section V.
II. CODEC IMAGE VIDEO
Figure 1 shows the subsystem of CoDec (Compressor/Decompressor) video system [2, 3]. It consists of a compressor and a decompressor. The compressor is made up of an image pre-processor, a discrete cosine
Manuscript received in April 30, 2009.
transform (DCT), a quantizer Vector (QV) and a Variable
Length Coding (VLC). The compressed image is then transmitted via a channel line or wirelessly to the decompressor. The decompressor consists of an Inverse Variable Length Coding (IVLC), an inverse discrete cosine transform (IDCT), an inverse quantizer (IQV), and a postprocessor
as shown in Figure 1.
Fig. 1. CoDec image video system.
Discrete Cosine Transform (DCT) block receives an NxN matrix image, which is divided into smaller image blocks (4x4, 8x8, 16x16, ...) where each block is transformed from the spatial domain to the frequency domain. DCT decomposes signal into spatial frequency components called DCT coefficients [2]. The lower frequency DCT coefficients appear toward the first line/first column of the DCT matrix, and the higher frequency coefficients are in the last line/last column of the DCT matrix. The quantization is used to discard insignificant data without introducing any artifacts to the image. After quantization, the majority of the DCT coefficients are equal to zero [4, 5]. A run-length coding
(RLC) and variable length coding (VLC) are used to retrieve
code words and their lengths from predefined lookup tables. The decompressor block is used to reconstruct the compressed image using the inverse process.
III. DCT HARDWARE DESIGN
A. Theory of DCT for Hardware Implementation Equation 1, shows the 1-D Discrete Cosine Transform where F(u): coefficient value in the transform domain, f(x): coefficient value in the pixel domain, x: spatial coordinate in the pixel domain, u: coordinate in the transform domain,
RESULTS
2D Discrete Cosine Transform can be implemented onto an FPGA through system generator using hardware models, which can be used as a building block for various image processing systems. System Generator works with standard Simulink models including “Gateway In” and “Gateway Out” defines the boundary of the FPGA. The input image is obtained by MATLAB and transformed into a matrix representation. This image is then decomposed into (8x8) block images. Figure 5 shows an 8x8 block image obtained from a 256x256 gray scale image.
CONCLUSION
We have presented the implementation of the 2D-DCT algorithm using LEE graph with combined pipeline architecture. This implementation was realized with a Xilinx XC3S500E Spartan-3E Starter FPGA, clocked at 50 MHz. The use of a reprogrammable device permits the continuing
parametric changes of the DCT in real time. The Xilinx System Generator, embedded in MATLAB Simulink was used to program the model and test in the FPGA board using the hardware co-simulation feature tools. Finally, the error percentages about 8 % of the grayscale pixel were very small between the images before the 2D-DCT implementation and after the hardware implementation.
[attachment=22555]
INTRODUCTION
large number of image data compression techniques areavailable, each one being adapted to a specific type of application, such as: compact disc, videoconference, videophone and multimedia systems. In all of these applications the transmission line bandwidth will determine
the compression standard to be used [1]. Among these, there is a compression technique based on a frequency transform called a Discrete Cosine Transform (DCT). This transform contains unique characteristics which allow for the creation of an efficient image compression; image and video compressors and decompressors are implemented in both
software and hardware. However, hardware implementations are especially important for the realization of highly parallel algorithms and can achieve much higher throughput than software solutions. The DCT transform was greatly enhanced by its implementation in VLSI circuits,
which are becoming increasingly faster. VLSI circuits are now capable of executing a DCT transform in real time. In this paper, we present the methodology to implement the DCT. The proposed system could be useful in many other applications that require image data compression. We describe in section II the general description of the codec image video system that required the data compression. The DCT hardware design implementations are subjects of section III. Section IV contains the implementation process of the DCT using FPGA and its experimental results. Finally, conclusion is given in section V.
II. CODEC IMAGE VIDEO
Figure 1 shows the subsystem of CoDec (Compressor/Decompressor) video system [2, 3]. It consists of a compressor and a decompressor. The compressor is made up of an image pre-processor, a discrete cosine
Manuscript received in April 30, 2009.
transform (DCT), a quantizer Vector (QV) and a Variable
Length Coding (VLC). The compressed image is then transmitted via a channel line or wirelessly to the decompressor. The decompressor consists of an Inverse Variable Length Coding (IVLC), an inverse discrete cosine transform (IDCT), an inverse quantizer (IQV), and a postprocessor
as shown in Figure 1.
Fig. 1. CoDec image video system.
Discrete Cosine Transform (DCT) block receives an NxN matrix image, which is divided into smaller image blocks (4x4, 8x8, 16x16, ...) where each block is transformed from the spatial domain to the frequency domain. DCT decomposes signal into spatial frequency components called DCT coefficients [2]. The lower frequency DCT coefficients appear toward the first line/first column of the DCT matrix, and the higher frequency coefficients are in the last line/last column of the DCT matrix. The quantization is used to discard insignificant data without introducing any artifacts to the image. After quantization, the majority of the DCT coefficients are equal to zero [4, 5]. A run-length coding
(RLC) and variable length coding (VLC) are used to retrieve
code words and their lengths from predefined lookup tables. The decompressor block is used to reconstruct the compressed image using the inverse process.
III. DCT HARDWARE DESIGN
A. Theory of DCT for Hardware Implementation Equation 1, shows the 1-D Discrete Cosine Transform where F(u): coefficient value in the transform domain, f(x): coefficient value in the pixel domain, x: spatial coordinate in the pixel domain, u: coordinate in the transform domain,
RESULTS
2D Discrete Cosine Transform can be implemented onto an FPGA through system generator using hardware models, which can be used as a building block for various image processing systems. System Generator works with standard Simulink models including “Gateway In” and “Gateway Out” defines the boundary of the FPGA. The input image is obtained by MATLAB and transformed into a matrix representation. This image is then decomposed into (8x8) block images. Figure 5 shows an 8x8 block image obtained from a 256x256 gray scale image.
CONCLUSION
We have presented the implementation of the 2D-DCT algorithm using LEE graph with combined pipeline architecture. This implementation was realized with a Xilinx XC3S500E Spartan-3E Starter FPGA, clocked at 50 MHz. The use of a reprogrammable device permits the continuing
parametric changes of the DCT in real time. The Xilinx System Generator, embedded in MATLAB Simulink was used to program the model and test in the FPGA board using the hardware co-simulation feature tools. Finally, the error percentages about 8 % of the grayscale pixel were very small between the images before the 2D-DCT implementation and after the hardware implementation.