21-05-2012, 01:06 PM
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding
[attachment=22557]
INTRODUCTION
WITH RAPID growth of multimedia services, the convolutional
turbo code (CTC) has been widely adopted
as one of forward error correcting (FEC) schemes of wireless
standards to have a reliable transmission over noisy channels.
Single-binary (SB) CTC, proposed in 1993 [1], has been the
well-known FEC code that can achieve high data rates and
coding gains close to the Shannon limit. The SB CTC code has
been adopted in the FEC schemes of wideband code division
multiple access (WCDMA) [2], high-speed downlink packet access
(HSDPA) [2], and long term evolution (LTE) [2]. In 1999,
non-binary CTC [3] was introduced to achieve superior performance
than the SB CTC.
1PW-1HW MAP Decoding
A straightforward way to achieve the alternative PW and
HW MAP decoding is to assemble one scalable MAP processor
of the PW MAP decoding and one scalable MAP processor
of the HW MAP decoding into a MAP processor. Hence,
the 1PW-1HW MAP decoding is proposed to alternatively
perform the PW and HW MAP decoding with shared computational
units and storages. Fig. 4 shows the architecture of
the 1PW-1HW MAP processor in PW and HW modes which
perform one parallel window of the PW MAP decoding shown
in Fig. 2(b) and one parallel window of the HW MAP decoding
shown in Fig. 3©. The decoding latency of the 1PW-1HW
MAP decoding achieves in PW mode and in HW mode.
PROPOSED AREA-EFFICIENT SCALABLE MAP DECODING
The aforementioned parallel processing techniques are the individualPWMAPdecoding
and individualHWMAPdecoding.
In this paper, we intend to propose area-efficient scalable MAP
processors which can alternatively operate on both the PW and
HW MAP decoding. In this section, three combinations of the
PW and HW MAP decoding are proposed.
[attachment=22557]
INTRODUCTION
WITH RAPID growth of multimedia services, the convolutional
turbo code (CTC) has been widely adopted
as one of forward error correcting (FEC) schemes of wireless
standards to have a reliable transmission over noisy channels.
Single-binary (SB) CTC, proposed in 1993 [1], has been the
well-known FEC code that can achieve high data rates and
coding gains close to the Shannon limit. The SB CTC code has
been adopted in the FEC schemes of wideband code division
multiple access (WCDMA) [2], high-speed downlink packet access
(HSDPA) [2], and long term evolution (LTE) [2]. In 1999,
non-binary CTC [3] was introduced to achieve superior performance
than the SB CTC.
1PW-1HW MAP Decoding
A straightforward way to achieve the alternative PW and
HW MAP decoding is to assemble one scalable MAP processor
of the PW MAP decoding and one scalable MAP processor
of the HW MAP decoding into a MAP processor. Hence,
the 1PW-1HW MAP decoding is proposed to alternatively
perform the PW and HW MAP decoding with shared computational
units and storages. Fig. 4 shows the architecture of
the 1PW-1HW MAP processor in PW and HW modes which
perform one parallel window of the PW MAP decoding shown
in Fig. 2(b) and one parallel window of the HW MAP decoding
shown in Fig. 3©. The decoding latency of the 1PW-1HW
MAP decoding achieves in PW mode and in HW mode.
PROPOSED AREA-EFFICIENT SCALABLE MAP DECODING
The aforementioned parallel processing techniques are the individualPWMAPdecoding
and individualHWMAPdecoding.
In this paper, we intend to propose area-efficient scalable MAP
processors which can alternatively operate on both the PW and
HW MAP decoding. In this section, three combinations of the
PW and HW MAP decoding are proposed.