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document describes the hardware and software architecture

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Components Used

The information in this document is based on this hardware version:
• Cisco 3600 Series Routers
The information in this document was created from the devices in a specific lab environment. All of the devices used in this document started with a cleared (default) configuration. If your network is live, make sure that you understand the potential impact of any command.

Background Information

The 3600 Series Routers include these models:
• 3620 equipped with two network module slots
• 3640 equipped with four network module slots
• 3660 equipped with six network module slots


Main Processor - CPU

• The processor loads instructions defined in Cisco IOS software from the main processor memory and executes them.
• The 3620 uses an 80 MHz IDT RISC Processor (R4700)
o Multiplexed 64-bit address and data bus
o Internal 16 KB data cache, 16 KB instruction cache, both 2-way set associative, write back
• The 3640 uses the same processor as the 3620, but with a 100 MHz internal clock.
• The 3660 uses a 225 MHz IDT RISC Processor (R5271) with 2 MB of Level 2 cache.

System Controller

The system controller helps the main processor with device control, interrupt handling, counting/timing, data transfer, and communication with slower Input/Output (I/O) devices, and dynamic RAM (DRAM). The system controller contains the cache, Flash, DRAM, PCI, and Interrupt controller.

PCI Bus

The PCI Bus is the medium of communication between the CPU and the network modules (NMs), mainly for packet data transfer.
• The PCI Bus is 32-bit, 20 Mhz for the 3620, and 25 MHz for the 3640 and 3660.
• The PCI Bridges (two on the 3640, three on the 3660) provide some isolation and allow inter PCI Bus communication. There is no bridge on the 3620; the NMs are connected directly.
• The Arbiter (not shown) controls the communication over the PCI Bus, and resolves master-slave conflicts.

Other Buses

Other buses are used by the CPU to access various components of the system and to transfer instructions and data to and from specified memory addresses.
• The CPU Bus is for high speed operations, with direct Processor access - 64-bit multiplexed, 40 MHz in the 3620, 50 MHz in the 3640, and 75 MHz in the 3660.
• The I/O Bus allows the System Controller to control other devices. It allows a 32-bit DRAM interface in the 3620; 32- or 64-bit DRAM interface in the 3640; and 64-bit SDRAM interface in the 3660.