29-05-2012, 12:24 PM
Design and Implementation of BSU for IFF Radar System using Xilinx
Vertex2Pro FPGA
[attachment=23308]
Abstract
Beam steering unit (BSU) is one of the important
subsystems of electronically scanned Antenna Array
(ESAA) and is responsible for electronically steering
the beam in a specified direction. The BSU receives the
signals like beam pointing angle or sector scan and
beam switching time from the signal processor of the
IFF radar system over a serial RS-422 interface. Based
on these input parameters it generates phase values for
the phase shifters connected to the antenna elements.
The switching of the beam from one position to the next
depends on the switching time of the digital phase
shifter.
Introduction
Beam steering unit (BSU) is one of the important
subsystems of the phased array radar [1]. It steers the
beam electronically in a particular direction. Electronic
scanning has various advantages over mechanical
scanning as there is no need to rotate the antenna
physically. The card has been designed and developed
to steer the phased array antenna electronically. In this
paper the BSU has been developed for electronically
steering a planar antenna array for secondary
surveillance radar commonly also known as IFF in
military application. The BSU is designed for an 8x4
element planar antenna array. The radiating elements
chosen for this phased array is printed dipole.
Design and development of BSU
BSU is designed and developed using state-of the art
technology involving Xilinx Vertex2Pro based
processor board and Phase shifter Interface Card (PIC)
consisting of digital differential receivers and latches.
The block diagram of the system is shown in Fig-1.
The interfacing between Vertex2Pro processor board
and Phase shifter Interface Card (PIC) is through ±49
bits of discrete differential signals. These 49 bits
consists of 48-bits of phase values and 01 bit to latch
the phase values to the phase shifters. The IFF signal
processor sends interrogation Mode signals to the
processor board for selecting transmit beam phase
values during transmission and receive beam phase
values during reception for a particular look angle or
sector scan mode. The processor board also receives the
beam-pointing angle and beam switching time
information on serial RS-422 interface and then using
serial controller passes this information to the processor
to generate the required phase values for each of the 8
phase shifters. The beam switching time depends on the
switching speed of digital phase shifter.
Hardware design
Hardware design of Vertex2Processor board:
The Vertex2Pro FPGA (XCV30) is having two
hardcore IBM Power PC and 30K logic cells for digital
logic inside the FPGA. A Vertex2Pro FPGA allows
making the design more adaptable to change and help
in minimizing the hardware. It also facilitates the
simplification of the debugging procedure. These
features reduce the design and implementation cycle.
The hardware design of the Vertex2Pro FPGA
(XCV2P30) based board is given in Fig-2. The block
diagram inside the FPGA is shown in Fig-3, The
custom logic is having the look-up table with control
logic.
Conclusion
The beam steering unit is realized by using of
IBM PowerPC and FPGA (both are on single chip). The
functional interface and timing requirements as per
specification are achieved. This hardware is integrated
and proven to show electronic scanning with phased
array antenna for IFF interrogator system.
Vertex2Pro FPGA
[attachment=23308]
Abstract
Beam steering unit (BSU) is one of the important
subsystems of electronically scanned Antenna Array
(ESAA) and is responsible for electronically steering
the beam in a specified direction. The BSU receives the
signals like beam pointing angle or sector scan and
beam switching time from the signal processor of the
IFF radar system over a serial RS-422 interface. Based
on these input parameters it generates phase values for
the phase shifters connected to the antenna elements.
The switching of the beam from one position to the next
depends on the switching time of the digital phase
shifter.
Introduction
Beam steering unit (BSU) is one of the important
subsystems of the phased array radar [1]. It steers the
beam electronically in a particular direction. Electronic
scanning has various advantages over mechanical
scanning as there is no need to rotate the antenna
physically. The card has been designed and developed
to steer the phased array antenna electronically. In this
paper the BSU has been developed for electronically
steering a planar antenna array for secondary
surveillance radar commonly also known as IFF in
military application. The BSU is designed for an 8x4
element planar antenna array. The radiating elements
chosen for this phased array is printed dipole.
Design and development of BSU
BSU is designed and developed using state-of the art
technology involving Xilinx Vertex2Pro based
processor board and Phase shifter Interface Card (PIC)
consisting of digital differential receivers and latches.
The block diagram of the system is shown in Fig-1.
The interfacing between Vertex2Pro processor board
and Phase shifter Interface Card (PIC) is through ±49
bits of discrete differential signals. These 49 bits
consists of 48-bits of phase values and 01 bit to latch
the phase values to the phase shifters. The IFF signal
processor sends interrogation Mode signals to the
processor board for selecting transmit beam phase
values during transmission and receive beam phase
values during reception for a particular look angle or
sector scan mode. The processor board also receives the
beam-pointing angle and beam switching time
information on serial RS-422 interface and then using
serial controller passes this information to the processor
to generate the required phase values for each of the 8
phase shifters. The beam switching time depends on the
switching speed of digital phase shifter.
Hardware design
Hardware design of Vertex2Processor board:
The Vertex2Pro FPGA (XCV30) is having two
hardcore IBM Power PC and 30K logic cells for digital
logic inside the FPGA. A Vertex2Pro FPGA allows
making the design more adaptable to change and help
in minimizing the hardware. It also facilitates the
simplification of the debugging procedure. These
features reduce the design and implementation cycle.
The hardware design of the Vertex2Pro FPGA
(XCV2P30) based board is given in Fig-2. The block
diagram inside the FPGA is shown in Fig-3, The
custom logic is having the look-up table with control
logic.
Conclusion
The beam steering unit is realized by using of
IBM PowerPC and FPGA (both are on single chip). The
functional interface and timing requirements as per
specification are achieved. This hardware is integrated
and proven to show electronic scanning with phased
array antenna for IFF interrogator system.