29-05-2012, 04:15 PM
EPIC ARCHITECTURE
[attachment=23388]
Introduction
EPIC- Explicitly Parallel Instruction Computing
Research for EPIC architecture began in early 1989, but the name EPIC was not given to architecture research until 1997 by hawlett Packard and Intel alliance.
IA-64 (Intel Architecture 64) was Intel’s first attempt at a 64-bit CPU architecture, and is based on EPIC.
The main goal of designing EPIC is to achieve high amounts of instruction level parallelism, but with a reduced amount of hardware complexity.
Motivations behind EPIC
Limitations to Superscalar ILP
– Data Hazards
• Data dependencies between instructions mean that these instructions cannot be executed correctly together.
– Control Hazards
• ILP identification requires several instructions to be pre- fetched to find parallel instruction pairs.
• Branches make this difficult. What if we pre-fetch from the wrong side of a branch?
– Memory Latencies
• Load-Use dependencies cause pipelines to stall.
• Stalled pipelines cannot execute further instructions till stall is resolved.
IA-64 architecture provides solution for all these problems.
The IA-64 architecture
Mainly designed for high performance computing.
scientific
technical
business
Itanium™ processor is the first implementation of IA-64.
[attachment=23388]
Introduction
EPIC- Explicitly Parallel Instruction Computing
Research for EPIC architecture began in early 1989, but the name EPIC was not given to architecture research until 1997 by hawlett Packard and Intel alliance.
IA-64 (Intel Architecture 64) was Intel’s first attempt at a 64-bit CPU architecture, and is based on EPIC.
The main goal of designing EPIC is to achieve high amounts of instruction level parallelism, but with a reduced amount of hardware complexity.
Motivations behind EPIC
Limitations to Superscalar ILP
– Data Hazards
• Data dependencies between instructions mean that these instructions cannot be executed correctly together.
– Control Hazards
• ILP identification requires several instructions to be pre- fetched to find parallel instruction pairs.
• Branches make this difficult. What if we pre-fetch from the wrong side of a branch?
– Memory Latencies
• Load-Use dependencies cause pipelines to stall.
• Stalled pipelines cannot execute further instructions till stall is resolved.
IA-64 architecture provides solution for all these problems.
The IA-64 architecture
Mainly designed for high performance computing.
scientific
technical
business
Itanium™ processor is the first implementation of IA-64.