29-05-2012, 04:34 PM
Implementation of Viterbi Encoder and Decoder on FPGA
[attachment=23395]
Abstract
In this project, Viterbi Encoder and Decoder is implemented on Sparten-3e FPGA. The
transmitter is of constraint length 3 and uses a two state encoder of rate 1/2. The
decoder implements trace back algorithm on a set of 16 bits of received sequence. The
Viterbi decoder can operate at a frequency of 82.7 MHz. It is implemented on FPGA
operation at a frequency of 50 MHz.
Introduction
Viterbi Algorithm
The Viterbi algorithm is commonly used in a wide range of communications and data
storage applications. The maximum likelihood detection of a digital stream is possible
by Viterbi algorithm. In general convolutional codes are decoded by Viterbi Algorithm.
Error Correction
For a rate 1/2 encoder with constraint length of 3, the code can correct upto 2 errors in
16 bits of transmitted data. Here it is assumed that errors do not occur in consecutively.
This report details the implementation of the algorithm.
1.3 Encoder Speci cations
Rate of Encoder
The code rate, is expressed as a ratio of the number of bits into the convolutional encoder
(k) to the number of channel symbols output by the convolutional encoder (n) in a given
encoder cycle. A rate 1/2 encoder is implemented in the design.
Constraint length (K)
The constraint length parameter, K, denotes the ”length” of the convolutional encoder,
i.e. how many k-bit stages are available to feed the combinatorial logic that produces
the output symbols. Closely related to K is the parameter m, which indicates how many
encoder cycles an input bit is retained and used for encoding after it first appears at the
input to the convolutional encoder.
Encoder Implementation
Convolutional Encoder shown in Fig. 1.1 takes input data bit and gives out two bits.
Convolutional encoding is a process of adding redundancy to a signal stream. It allows
variable code rates(1/2), constraint lengths(K=3) and generator polynomials. To convolutionally
encode data, start with 2 memory registers, each holding 1 input bit. Registers
start with a value of 0. The encoder has 2 modulo-2 adders which is implemented with
a XOR gate. It generates 2 bit polynomials, one for each adder.
Implementation Options of Decoder on Hard-
ware
In Viterbi decoder, there are two known memory organization techniques for the storage
of survivor sequences from which the decoded information sequence is retrieved, namely
register exchange method and trace back method. The register exchange method is good
for codes with small number of States and small truncation length of the trellis, while the
trace-back methods are more suitable for codes having many states and long truncation
lengths. Since the design uses decode of code of length 16 bits, trace-back method is
choosen.
[attachment=23395]
Abstract
In this project, Viterbi Encoder and Decoder is implemented on Sparten-3e FPGA. The
transmitter is of constraint length 3 and uses a two state encoder of rate 1/2. The
decoder implements trace back algorithm on a set of 16 bits of received sequence. The
Viterbi decoder can operate at a frequency of 82.7 MHz. It is implemented on FPGA
operation at a frequency of 50 MHz.
Introduction
Viterbi Algorithm
The Viterbi algorithm is commonly used in a wide range of communications and data
storage applications. The maximum likelihood detection of a digital stream is possible
by Viterbi algorithm. In general convolutional codes are decoded by Viterbi Algorithm.
Error Correction
For a rate 1/2 encoder with constraint length of 3, the code can correct upto 2 errors in
16 bits of transmitted data. Here it is assumed that errors do not occur in consecutively.
This report details the implementation of the algorithm.
1.3 Encoder Speci cations
Rate of Encoder
The code rate, is expressed as a ratio of the number of bits into the convolutional encoder
(k) to the number of channel symbols output by the convolutional encoder (n) in a given
encoder cycle. A rate 1/2 encoder is implemented in the design.
Constraint length (K)
The constraint length parameter, K, denotes the ”length” of the convolutional encoder,
i.e. how many k-bit stages are available to feed the combinatorial logic that produces
the output symbols. Closely related to K is the parameter m, which indicates how many
encoder cycles an input bit is retained and used for encoding after it first appears at the
input to the convolutional encoder.
Encoder Implementation
Convolutional Encoder shown in Fig. 1.1 takes input data bit and gives out two bits.
Convolutional encoding is a process of adding redundancy to a signal stream. It allows
variable code rates(1/2), constraint lengths(K=3) and generator polynomials. To convolutionally
encode data, start with 2 memory registers, each holding 1 input bit. Registers
start with a value of 0. The encoder has 2 modulo-2 adders which is implemented with
a XOR gate. It generates 2 bit polynomials, one for each adder.
Implementation Options of Decoder on Hard-
ware
In Viterbi decoder, there are two known memory organization techniques for the storage
of survivor sequences from which the decoded information sequence is retrieved, namely
register exchange method and trace back method. The register exchange method is good
for codes with small number of States and small truncation length of the trellis, while the
trace-back methods are more suitable for codes having many states and long truncation
lengths. Since the design uses decode of code of length 16 bits, trace-back method is
choosen.