30-05-2012, 11:53 AM
Intelligent Random Access Memory
[attachment=23477]
IRAM Vision Statement
Microprocessor & DRAM on a single chip:
On-chip memory latency 5-10X, bandwidth 50-100X
Improve energy efficiency 2X-4X (No off-chip bus)
Serial I/O 5-10X v. buses
Smaller board area/volume
Outline
Today’s Situation: Microprocessor
Today’s Situation: DRAM
IRAM Opportunities
Potential Advantages of IRAM
IRAM Architecture Options
IRAM Challenges
The Memory-Processor Gap
Most techniques focus on latency tolerance which exposes bandwidth limitations
The most obvious solution is to reduce traffic to off-chip memory
Processor speed increases by 60% per year while memory access speed increase is 10%
Today’s Situation: Microprocessor
Rely on caches to bridge gap
Microprocessor-DRAM performance gap
Time of a full cache miss in instructions executed
2nd Alpha (8400): 266 ns/3.3 ns = 80 clks x 4 or 320 ns
1st Alpha (7000): 340 ns/5.0 ns = 68 clks x 2 or 136 ns
3rd Alpha (t.b.d.): 180 ns/1.7 ns =108 clks x 6 or 648 ns
X latency x 3X clock rate x 3X Instr/clock => - 5X
Power limits performance (battery, cooling)
Shrinking number of desktop ISAs?
No more PA-RISC; questionable future for MIPS and Alpha
Future dominated by IA-64?
[attachment=23477]
IRAM Vision Statement
Microprocessor & DRAM on a single chip:
On-chip memory latency 5-10X, bandwidth 50-100X
Improve energy efficiency 2X-4X (No off-chip bus)
Serial I/O 5-10X v. buses
Smaller board area/volume
Outline
Today’s Situation: Microprocessor
Today’s Situation: DRAM
IRAM Opportunities
Potential Advantages of IRAM
IRAM Architecture Options
IRAM Challenges
The Memory-Processor Gap
Most techniques focus on latency tolerance which exposes bandwidth limitations
The most obvious solution is to reduce traffic to off-chip memory
Processor speed increases by 60% per year while memory access speed increase is 10%
Today’s Situation: Microprocessor
Rely on caches to bridge gap
Microprocessor-DRAM performance gap
Time of a full cache miss in instructions executed
2nd Alpha (8400): 266 ns/3.3 ns = 80 clks x 4 or 320 ns
1st Alpha (7000): 340 ns/5.0 ns = 68 clks x 2 or 136 ns
3rd Alpha (t.b.d.): 180 ns/1.7 ns =108 clks x 6 or 648 ns
X latency x 3X clock rate x 3X Instr/clock => - 5X
Power limits performance (battery, cooling)
Shrinking number of desktop ISAs?
No more PA-RISC; questionable future for MIPS and Alpha
Future dominated by IA-64?