30-05-2012, 01:52 PM
FPGA Design
[attachment=23531]
FPGA Design
The primary objective of this day of training is to make participants proficient in the process of
developing, downloading and running an FPGA design on the Desktop NanoBoard. We will go
through the FPGA design framework and demonstrate just how simple FPGA design is with Altium
Designer.
Learning objectives
· To be competent in developing FPGA designs using standard FPGAbased
libraries and the
schematic capture environment
· To understand and be able to make use of the FPGA build process
· To be familiar with the peripheral capabilities of the Desktop NanoBoard and know how to
incorporate their use in custom FPGA designs.
· To appreciate the different communication mechanisms used by the software to control and probe
a running FPGA design.
· To be competent with the use of virtual instruments in an FPGA design.
A quick word about projects and design workspaces
To the uninitiated, Altium Designer projects may appear a little
confusing; especially when projects contain other projects.
The important thing to remember is that each project can only
have one output. If you have a design that requires several
PCBs then you will need a separate PCB project for each
PCB. If you have a design that uses several FPGAs then you
will also need a separate FPGA project for each FPGA used
on the final design.
Projects that are related together in some way can be grouped
together using a type of ‘super project’ called a Design
Workspace. Design Workspaces are simply a convenient
way of packaging one or more projects together so that all
projects from a single design can be opened together.
Altium Designer supports a fully hierarchical design approach.
As such it is possible for some projects to contain other
projects within them.
Wiring the design
Connectivity between the component pins is created by physical connectivity, or logical connectivity.
Placing wires that connect component pins to each other creates physical connectivity. Matching net
identifiers such as net labels, power ports, ports and sheet entries creates logical connectivity. When
the design is compiled the connectivity is established, according to the net identifier scope defined
for the project.
Note that while the environment supports compiling projects using either a flat or hierarchical
connective structure, FPGA projects must be hierarchical.
[attachment=23531]
FPGA Design
The primary objective of this day of training is to make participants proficient in the process of
developing, downloading and running an FPGA design on the Desktop NanoBoard. We will go
through the FPGA design framework and demonstrate just how simple FPGA design is with Altium
Designer.
Learning objectives
· To be competent in developing FPGA designs using standard FPGAbased
libraries and the
schematic capture environment
· To understand and be able to make use of the FPGA build process
· To be familiar with the peripheral capabilities of the Desktop NanoBoard and know how to
incorporate their use in custom FPGA designs.
· To appreciate the different communication mechanisms used by the software to control and probe
a running FPGA design.
· To be competent with the use of virtual instruments in an FPGA design.
A quick word about projects and design workspaces
To the uninitiated, Altium Designer projects may appear a little
confusing; especially when projects contain other projects.
The important thing to remember is that each project can only
have one output. If you have a design that requires several
PCBs then you will need a separate PCB project for each
PCB. If you have a design that uses several FPGAs then you
will also need a separate FPGA project for each FPGA used
on the final design.
Projects that are related together in some way can be grouped
together using a type of ‘super project’ called a Design
Workspace. Design Workspaces are simply a convenient
way of packaging one or more projects together so that all
projects from a single design can be opened together.
Altium Designer supports a fully hierarchical design approach.
As such it is possible for some projects to contain other
projects within them.
Wiring the design
Connectivity between the component pins is created by physical connectivity, or logical connectivity.
Placing wires that connect component pins to each other creates physical connectivity. Matching net
identifiers such as net labels, power ports, ports and sheet entries creates logical connectivity. When
the design is compiled the connectivity is established, according to the net identifier scope defined
for the project.
Note that while the environment supports compiling projects using either a flat or hierarchical
connective structure, FPGA projects must be hierarchical.