02-06-2012, 11:44 AM
Designing Polyphase DPD Solutions with 28-nm FPGAs
[attachment=23956]
Introduction
The ever-increasing use of smart phones and devices is driving exponential growth in
mobile data traffic. As Figure 1 shows, mobile networks will soon approach 4000
petabytes per month.
Source:
(1) Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, Cisco, 9 February 2010
Because the current mobile infrastructure cannot keep pace with the growing
demand, basestation providers need to upgrade their digital front end (DFE) radio
equipment to support wider and wider RF bandwidths. In addition, increasing
pressure on operators to reduce operating expenses (OPEX) and the trend towards
green technology are driving the need for more power-efficient solutions in the DFE
radio head.
DPD Background
In the modern radio access networks (RANs), improving the power efficiency of the
system is increasingly important. This improved efficiency is driven by the trend
towards green technologies, as well as providing a reduction of operating expenses
occurred with service operators through lower cooling costs and power bills. Due to
the technical difficulties of designing high-power linear power amplifiers (PAs), DPD
techniques are often used to compensate for the non-linearity of PAs. The DPD
technology aims to increase the efficiency of the PA by enabling it to be operated in
the saturated region (non-linear region) without introducing unacceptable
performance degradation. The popularity of DPD technology is mainly derived by
the lower cost of implementation and flexibility in comparison to other methods such
as feed-forward. Because the bandwidth of a pre-distorted signal is much higher
(typically at least five times) than the transmitted signal bandwidth, one of the
greatest challenges in FPGA-based DPD implementation is to meet the increasingly
large bandwidths with the FPGA fabric’s limited speed performance, while keeping
the resource usage as low as possible.
DPD Model in Detail
This section provides a more in-depth look at the DPD, including an overview of the
feed-forward path architecture and its implementation for targeting the Voltera series
model. The DPD operation is undertaken in baseband, and as shown in Figure 3, it
consists of two main parts: the feed-forward predistorter and the adaption module.
The predistorter models the inverse of PA behavior. When considering high sample
rates and increased computational complexity, a hardware-mapped implementation
of the predistorter is the only available option. The adaption block is responsible for
the estimation and update of the PA behavioral model parameters used in the
predistorter. The data captured from transmitter, , and observation receiver, , are
assumed to be aligned.
Polyphase DPD Feed-Forward Path Architecture
As mentioned before, when the signal bandwidth is higher than the FPGA maximum
achieved clock frequency, a single processing DPD feed-forward path is not sufficient
to handle the streaming data throughput. In this case, a polyphase feed-forward path
structure should be used.
Figure 5 illustrates a high-level conceptual block diagram of a polyphase path DPD
feed-forward path. The incoming data are separated into two subsets, the even
samples and the odd samples, each of which is carried by one delay chain. Hence, the
throughput of each chain is halved compared to the single chain design. For example,
if the transmitted signal bandwidth is 60 MHz, the predistorted bandwidth is
approximately 300 MHz to 420 MHz, resulting in 300 Msps to 420 Msps of data
throughput and then requiring 150-Msps to 210-Msps processing capability in each of
the polyphase chains. Hence, this structure becomes friendly to the FPGA fMAX. At the
end of the pre-distortion, the separated data streams will recombine together with the
aid of the SERDES in the FPGA. Identical processing results will be obtained but the
design only needs to run at half the frequency of the non-polyphase architecture at the
cost of paralleled operations, resulting in greater resource consumption. Hence it is
necessary to understand the implication on resource and power imposed by
introducing the polyphase DPD architecture.
[attachment=23956]
Introduction
The ever-increasing use of smart phones and devices is driving exponential growth in
mobile data traffic. As Figure 1 shows, mobile networks will soon approach 4000
petabytes per month.
Source:
(1) Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, Cisco, 9 February 2010
Because the current mobile infrastructure cannot keep pace with the growing
demand, basestation providers need to upgrade their digital front end (DFE) radio
equipment to support wider and wider RF bandwidths. In addition, increasing
pressure on operators to reduce operating expenses (OPEX) and the trend towards
green technology are driving the need for more power-efficient solutions in the DFE
radio head.
DPD Background
In the modern radio access networks (RANs), improving the power efficiency of the
system is increasingly important. This improved efficiency is driven by the trend
towards green technologies, as well as providing a reduction of operating expenses
occurred with service operators through lower cooling costs and power bills. Due to
the technical difficulties of designing high-power linear power amplifiers (PAs), DPD
techniques are often used to compensate for the non-linearity of PAs. The DPD
technology aims to increase the efficiency of the PA by enabling it to be operated in
the saturated region (non-linear region) without introducing unacceptable
performance degradation. The popularity of DPD technology is mainly derived by
the lower cost of implementation and flexibility in comparison to other methods such
as feed-forward. Because the bandwidth of a pre-distorted signal is much higher
(typically at least five times) than the transmitted signal bandwidth, one of the
greatest challenges in FPGA-based DPD implementation is to meet the increasingly
large bandwidths with the FPGA fabric’s limited speed performance, while keeping
the resource usage as low as possible.
DPD Model in Detail
This section provides a more in-depth look at the DPD, including an overview of the
feed-forward path architecture and its implementation for targeting the Voltera series
model. The DPD operation is undertaken in baseband, and as shown in Figure 3, it
consists of two main parts: the feed-forward predistorter and the adaption module.
The predistorter models the inverse of PA behavior. When considering high sample
rates and increased computational complexity, a hardware-mapped implementation
of the predistorter is the only available option. The adaption block is responsible for
the estimation and update of the PA behavioral model parameters used in the
predistorter. The data captured from transmitter, , and observation receiver, , are
assumed to be aligned.
Polyphase DPD Feed-Forward Path Architecture
As mentioned before, when the signal bandwidth is higher than the FPGA maximum
achieved clock frequency, a single processing DPD feed-forward path is not sufficient
to handle the streaming data throughput. In this case, a polyphase feed-forward path
structure should be used.
Figure 5 illustrates a high-level conceptual block diagram of a polyphase path DPD
feed-forward path. The incoming data are separated into two subsets, the even
samples and the odd samples, each of which is carried by one delay chain. Hence, the
throughput of each chain is halved compared to the single chain design. For example,
if the transmitted signal bandwidth is 60 MHz, the predistorted bandwidth is
approximately 300 MHz to 420 MHz, resulting in 300 Msps to 420 Msps of data
throughput and then requiring 150-Msps to 210-Msps processing capability in each of
the polyphase chains. Hence, this structure becomes friendly to the FPGA fMAX. At the
end of the pre-distortion, the separated data streams will recombine together with the
aid of the SERDES in the FPGA. Identical processing results will be obtained but the
design only needs to run at half the frequency of the non-polyphase architecture at the
cost of paralleled operations, resulting in greater resource consumption. Hence it is
necessary to understand the implication on resource and power imposed by
introducing the polyphase DPD architecture.