02-06-2012, 03:04 PM
A Compact AES Encryption Core on Xilinx FPGA
[attachment=24017]
Abstract:
Encryption has become a significant aspect of all types of communication networks. provides safe transmission through insecure path and also prevents data from being attacked by the offenders who try to intimidate the privacy and confidentiality of our critical data. So a reliable and secure transmission is one oftoday's challenges.
This paper presents an Advanced Encryption Standard (AES) encryption core on Field Programmable Gate Array (FPGA). The target device is Spartan-3 FPGA. We have designed an efficient and compact, iterative architecture with input and key, both of 128 bits. The throughput achieved is 2640.3712Mbps with a frequency of 206.28 MHz; using 8 embedded Block RAMs (DRAMs) and 390 Slices. The aim is to provide a fast encryption core for small size and low cost applications.
The chip is going to be coded using HDL then functional simulation will be performed and the code will be synthesized and logic simulation will be performed. Then timing simulation will be done to check the complete functionality and design specifications.
DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.
ADVANTAGES: Low Power, Low cost, Small device foot print, Long battery life, System on Chip Implementation
[attachment=24017]
Abstract:
Encryption has become a significant aspect of all types of communication networks. provides safe transmission through insecure path and also prevents data from being attacked by the offenders who try to intimidate the privacy and confidentiality of our critical data. So a reliable and secure transmission is one oftoday's challenges.
This paper presents an Advanced Encryption Standard (AES) encryption core on Field Programmable Gate Array (FPGA). The target device is Spartan-3 FPGA. We have designed an efficient and compact, iterative architecture with input and key, both of 128 bits. The throughput achieved is 2640.3712Mbps with a frequency of 206.28 MHz; using 8 embedded Block RAMs (DRAMs) and 390 Slices. The aim is to provide a fast encryption core for small size and low cost applications.
The chip is going to be coded using HDL then functional simulation will be performed and the code will be synthesized and logic simulation will be performed. Then timing simulation will be done to check the complete functionality and design specifications.
DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.
ADVANTAGES: Low Power, Low cost, Small device foot print, Long battery life, System on Chip Implementation