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DESIGN AND IMPLEMENTATION OF A CAN CONTROLLER ON FPGA.

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ABSTRACT:

In this article is present a stand-alone controller for the controller area network (CAN) protocol. The design contains all necessary features required to implement a high performance communication protocol. The CAN controller with a simple bus line connection performs all the functions of the physical and data-link layers. The application layer is provided by a microcontroller, to which the CAN controller connects through general purpose non-multiplexed parallel 8-bits bus.
The chip is going to be coded using HDL then functional simulation will be performed, then the code will be synthesized and logic simulation will be performed. Then place and route will be done and fitted on to Spartan-3E FPGA. Then timing simulation will be done to check the complete functionality and design specifications.
The complete chip functionality is going to be demonstrated on Spartan-3E FPGA.

SOFTWARE: VHDL.
DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.
TARGET DEVICE: SPARTAN-3E DEVICE FROM XILINX.
APPLICATIONS: The development of increasingly complex Microsystems requires the usage of a powerful field bus system for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.
ADVANTAGES: Low Power, Low cost, small device foot print, long battery life, System on Chip Implementation.

In the past, CAN-based products used a standard CAN controller chip, a microprocessor with an integrated CAN interface, or a custom ASIC with a CAN interface for high-volume applications. Now, with advances in silicon technologies, a new option is readily available: Field Programmable Gate Arrays (FPGA). An FPGA is a gate array that can be programmed during production or later when deployed. They occur at a high volume, which reduces the individual cost of the device. FPGA vendors announce their largest multi-million-device "system gates". Although few applications really require them, they allow other products to be implemented. Large devices need the most advanced silicon processing technologies. Since each FPGA family comprises several members ranging from large to small door beads, small devices are available in the same technology. With the high gate density available in these advanced process technologies, even small devices provide sufficient resources for system integrations. Suddenly, small FPGAs offer solutions that were not available before and cost only a few dollars.

The design contains all the necessary features necessary to implement a high performance communication protocol. The CAN controller with a single bus line connection performs all the functions of the physical and data link layers. The application layer is provided by a microcontroller, to which the CAN controller is connected through a non-multiplexed, general purpose 8-bit bus. The CAN communication protocol describes the method by which information is passed between devices. It fits the open system interconnect model, which is defined in terms of layers. Each layer of a device apparently communicates with the same layer on another device. The actual communication is between adjacent layers on each device and the devices are only connected by the physical medium through the physical layer of the model. The CAN architecture defines the two lowest layers of the model: the data link and the physical layers. Application levels are linked to the physical environment by layers of several emerging protocols, dedicated to particular industrial areas plus any number of ownership schemes defined by individual users of the CAN.

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