02-06-2012, 03:11 PM
Design and implementation of DMA controller
[attachment=24019]
ABSTRACT
A direct memory access (DMA) controller having memory to memory data transfer capability, a programmable wait state, a buffer chaining mode data transfer capability, a cascade master mode, separate channels for internal and external devices, and a programmable 8 or 16 bit requester bus size.
The DMA controller includes a channel circuit connected to transfer data to and from a port, a CPU interface, a bus connected to the channel circuit and to the CPU interface to transfer data there between, a state machine which generates a clock signal that is used for transferring data from the channel circuit across the bus to the CPU interface, the state machine having a programmable wait state which delays the transfer of data for a preprogrammable wait state which delays the transfer of data for a preprogrammed number of clock cycles, and a data mode register which is used for setting the preprogrammed number of clock cycles.
SOFTWARE: VHDL.
DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.
TARGET DEVICE: SPARTAN-3E DEVICE FROM XILINX.
[attachment=24019]
ABSTRACT
A direct memory access (DMA) controller having memory to memory data transfer capability, a programmable wait state, a buffer chaining mode data transfer capability, a cascade master mode, separate channels for internal and external devices, and a programmable 8 or 16 bit requester bus size.
The DMA controller includes a channel circuit connected to transfer data to and from a port, a CPU interface, a bus connected to the channel circuit and to the CPU interface to transfer data there between, a state machine which generates a clock signal that is used for transferring data from the channel circuit across the bus to the CPU interface, the state machine having a programmable wait state which delays the transfer of data for a preprogrammable wait state which delays the transfer of data for a preprogrammed number of clock cycles, and a data mode register which is used for setting the preprogrammed number of clock cycles.
SOFTWARE: VHDL.
DEVELOPMENT TOOLS: XILINX ISE, MODELSIM, CHIPSCOPE.
TARGET DEVICE: SPARTAN-3E DEVICE FROM XILINX.