02-06-2012, 03:19 PM
DEVELOPMENT OF FPGA BASED PCI BUS ARBITER MULTIPROCESSOR ENVIRONMENT
[attachment=24023]
ABSTRACT
This PCI bus arbiter any PCI system may have one or more PCI-master devices. Most devices can behave as target hosts, but one must be a PCI-bus initiator, or master. Normally, only microprocessors or high-level DSPs perform both PCI master and target modes, and they may include a PCI arbiter.
It performs an arbitration function by enabling access to the PCI bus depending on the predetermined priorities of each PCI device.
In a multiprocessor environment, several processors share the same system bus such as a PCI bus. A system based on multiprocessors can work in a coordinated manner only if bus arbitration is in force. The PCI Bus Arbiter design is for arbitrating four processors, some of which can be configured as the masters and others as targets. As an illustration, we will consider an application such as a video compression system for bus arbitration, although the design can be modified or extended to any other multiprocessor application and bus. Sharing the PCI bus are four masters, namely:
• Video Grabber, which will input a raw video data. It can be NTSC, PAL or SECAM sequence or may be in XGA, SVGA or in any other format. Any color motion picture can be processed, say, at 30 frames per second or 25 frames per second. Using the PCI, we can input the raw data into the VideoCodec.
• Video Codec brings about the compression and reconstruction. We have an encoder and a decoder in the Codec, which brings about respectively the compression and decompression. This has to be designed in Verilog and implemented on either FPGA or ASIC.
• Fire Wire is a serial bus, which can be connected up to 64K nodes. It serializes the compressed data and broadcasts the compressed bit stream. Concurrently, it can receive a compressed bit stream from external source and send it to the decoder in Video Codec for effecting decompression.
• CPU (PC), which configures and coordinates the system activities via a north bridge.
[attachment=24023]
ABSTRACT
This PCI bus arbiter any PCI system may have one or more PCI-master devices. Most devices can behave as target hosts, but one must be a PCI-bus initiator, or master. Normally, only microprocessors or high-level DSPs perform both PCI master and target modes, and they may include a PCI arbiter.
It performs an arbitration function by enabling access to the PCI bus depending on the predetermined priorities of each PCI device.
In a multiprocessor environment, several processors share the same system bus such as a PCI bus. A system based on multiprocessors can work in a coordinated manner only if bus arbitration is in force. The PCI Bus Arbiter design is for arbitrating four processors, some of which can be configured as the masters and others as targets. As an illustration, we will consider an application such as a video compression system for bus arbitration, although the design can be modified or extended to any other multiprocessor application and bus. Sharing the PCI bus are four masters, namely:
• Video Grabber, which will input a raw video data. It can be NTSC, PAL or SECAM sequence or may be in XGA, SVGA or in any other format. Any color motion picture can be processed, say, at 30 frames per second or 25 frames per second. Using the PCI, we can input the raw data into the VideoCodec.
• Video Codec brings about the compression and reconstruction. We have an encoder and a decoder in the Codec, which brings about respectively the compression and decompression. This has to be designed in Verilog and implemented on either FPGA or ASIC.
• Fire Wire is a serial bus, which can be connected up to 64K nodes. It serializes the compressed data and broadcasts the compressed bit stream. Concurrently, it can receive a compressed bit stream from external source and send it to the decoder in Video Codec for effecting decompression.
• CPU (PC), which configures and coordinates the system activities via a north bridge.