PRESENTED BY:
ARUN KUMAR PANDEY
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INTRODUCTION
SILICON ON INSULATOR (S.O.I.) is a new chip-fabrication technology you might think of as a "chip in a blanket."
Silicon-on-insulator (SOI) chips are made with a layer of silicon dioxide insulation that separates individual transistors from the underlying silicon wafer. In conventional CMOS chips, transistors sit in direct contact with the wafer. SOI's hair-thin blanket of silicon dioxide helps keep electrons flowing efficiently from one transistor gate to another without letting stray electrons leak out into the substrate. The result is a microprocessor in which electrons get to their destinations faster. These chips provide better processing performance; and SOI-based computers use less power because there's no waste due to leaked electrons.
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improve performance. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for improved performance and diminished short channel effects in microelectronics devices.
Silicon on Insulator (SOI) substrates are being increasingly used in MEMS applications, with the insulating layers serving as etch stop/sacrificial layers and/or device function layers. Apart from the conventional etching requirements including high etch rate, high selectivity and smooth sidewall, satisfactory etching of SOI wafers requires no notching at the silicon/insulator interface.
WHAT IS SOI ?
Increased demand for High Performance, Low Power and Low Area among microelectronic devices is continuously pushing the fabrication process to go beyond ultra deep sub-micron (UDSM) technologies such as 45nm, 32nm and so on. Currently, chips are being designed in 55nm, 45nm and 32nm process nodes. The performance and power goals for certain applications in these advanced nodes couldn’t be achieved with conventional silicon (bulk CMOS) process leading to an alternative, Silicon On Insulator (SOI) process. Silicon On Insulator fabrication process helps in achieving greater performance and offers less power consumption compared to the Bulk Process.
In a Silicon On Insulator (SOI) Fabrication technology Transistors are built on a silicon layer resting on an Insulating Layer of Silicon dioxide (SiO2). The insulating layer is created by flowing oxygen onto a plain silicon wafer and then heating the wafer to oxidize the silicon, thereby creating a uniform buried layer of silicon dioxide. Transistors are encapsulated in SiO2 on all sides. The below figure shows a typical
NMOS Transistor with Bulk CMOS Process and with SOI Process.
The insulating layer increases device performance by reducing junction capacitance as the junction is isolated from bulk silicon. The decrease in junction capacitance also reduces overall power consumption.
WHY SILICON-ON-INSULATORS ?
To enhance the performance of Si-devices, SOI is considered, especially when recognizing that only a thin layer from a face of the wafer is used for making the electronic components; the rest essentially serves as a mechanical support.
The major role of SOI is to electronically insulate a fine layer of the mono-crystalline silicon from the rest of the silicon wafer, beside the ever growing role of W.G.
Embedded layer of insulation enables the SOI-based chips to function at significantly higher speeds (30 to 40% more) while reducing electrical losses. The result is an increase in performance and a reduction in power consumption by up to up to 50%
Circuits built in SOI wafers have reduced parasitic capacitance when compared to bulk or epi-wafers.
Useful for space application as they are immune to radiation-induced single event upset (SEU).
Free of latch-up.
Number of masks are reduced by as much as 30%.
FABRICATION OF SOI
Fabrication steps are simpler and less complex :
• Fewer masks and ion implantation steps, made possible by the elimination of well and field isolation implants
• Less complex (costly) lithography and etching required to achieve next-generation performance
Some fabrication process :
- SOS – Silicon-on-Sapphire
- SIMOX – Separation by Implantation of Oxygen
- ZMR – Zone melting and recrystallization
- BESOI – Bond and Etch-back SOI
- Smart-cut SOI Technology
- SIMON (Separation by IMplantation Of Nitrogen)
1. SIMOX - Separation by Implantation of Oxygen
Ion implantation is a materials engineering process by which ions of a material are accelerated in an electrical field and impacted into another solid. This process is used to change the physical, chemical, or electrical properties of the solid. Ion implantation is used in semiconductor device fabrication and in metal finishing, as well as various applications in materials science research. The ions can introduce both a chemical change in the target, in that they can introduce a different element than the target or induce a nuclear transmutation, and a structural change, in that the crystal structure of the target can be damaged or even destroyed by the energetic collision cascades.
One prominent method for preparing silicon on insulator (SOI) substrates from conventional silicon substrates is the SIMOX (Separation by IMplantation of OXygen) process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high temperature annealing process.
Ion implantation equipment typically consists of an ion source, where ions of the desired element are produced, an accelerator, where the ions are electrostatically accelerated to a high energy, and a target chamber, where the ions impinge on a target, which is the material to be implanted. Thus ion implantation is a special case of particle radiation. Each ion is typically a single atom or molecule, and thus the actual amount of material implanted in the target is the integral over time of the ion current. This amount is called the dose. The currents supplied by implanters are typically small (microamperes), and thus the dose which can be implanted in a reasonable amount of time is small. Therefore, ion implantation finds application in cases where the amount of chemical change required is small.
2. Smart-cut SOI Technology
Smart Cut is a technological process that enables the transfer of very fine layers of crystalline material onto a mechanical support. The application of this technological procedure is used mainly in silicon-on-insulator (SOI). The role of SOI is to electronically insulate a fine layer of monocrystalline silicon from the rest of the silicon wafer; an ultra-thin silicon film is transferred to a mechanical support, thereby introducing an intermediate, insulating layer.