12-06-2012, 03:47 PM
BASIC PHYSICAL DESIGN AN OVERVIEW
[attachment=24216]
The preceding lectures have already given you the information of the different layers,
their representation (colour,hatching)etc. When the devices are represented using
these layers, we call it physical design. The design is carried out using the design tool,
which requires to follow certain rules. Physical structure is required to study the
impact of moving from circuit to layout. When we draw the layout from the
schematic, we are taking the first step towards the physical design.
CMOS STANDARD CELL DESIGN
Geometric regularity is very important to maintain some common electrical
characteristics between the cells in the library. The common physical limitation is to
fix the height and vary the width according to the required function. The Wp and Wn
are fixed considering power dissipation, propagation delay, area and noise immunity.
The best thing to do is to fix a required objective function and then fix Wn and Wp to
obtain the required objective
Usually in CMOS Wn is made equal to Wp . In the process of designing these gates
techniques may be employed to automatically generate the gates of common size.
Later optimization can be carried out to achieve a specific feature. Gate array layout
and sea of gate layout are constructed using the above techniques. The gate arrays
may be customized by having routing channels in between array of gates. The gate
array and the sea of gates have some special layout considerations. The gate arrays
use fixed image of the under layers i.e the diffusion and poly are fixed and metal are
programmable. The wiring layers are discretionary and providing the personalization
of the array. The rows of transistors are fixed and the routing channels are provided
in between them. Hence the design issues involves size of transistors, connectivity of
poly and the number of routing channels required.
CMOS LOGIC STRUCTURES
The various application that require logic structures have different optimizations.
Some of the circuit need fast response, some slow but very precise response, others
may need large functionality in a small space and so on. The CMOS logic structures
can be implemented in alternate ways to get specific optimization. These
optimizations are specific because of the trade off between the n number of design
parameters.
[attachment=24216]
The preceding lectures have already given you the information of the different layers,
their representation (colour,hatching)etc. When the devices are represented using
these layers, we call it physical design. The design is carried out using the design tool,
which requires to follow certain rules. Physical structure is required to study the
impact of moving from circuit to layout. When we draw the layout from the
schematic, we are taking the first step towards the physical design.
CMOS STANDARD CELL DESIGN
Geometric regularity is very important to maintain some common electrical
characteristics between the cells in the library. The common physical limitation is to
fix the height and vary the width according to the required function. The Wp and Wn
are fixed considering power dissipation, propagation delay, area and noise immunity.
The best thing to do is to fix a required objective function and then fix Wn and Wp to
obtain the required objective
Usually in CMOS Wn is made equal to Wp . In the process of designing these gates
techniques may be employed to automatically generate the gates of common size.
Later optimization can be carried out to achieve a specific feature. Gate array layout
and sea of gate layout are constructed using the above techniques. The gate arrays
may be customized by having routing channels in between array of gates. The gate
array and the sea of gates have some special layout considerations. The gate arrays
use fixed image of the under layers i.e the diffusion and poly are fixed and metal are
programmable. The wiring layers are discretionary and providing the personalization
of the array. The rows of transistors are fixed and the routing channels are provided
in between them. Hence the design issues involves size of transistors, connectivity of
poly and the number of routing channels required.
CMOS LOGIC STRUCTURES
The various application that require logic structures have different optimizations.
Some of the circuit need fast response, some slow but very precise response, others
may need large functionality in a small space and so on. The CMOS logic structures
can be implemented in alternate ways to get specific optimization. These
optimizations are specific because of the trade off between the n number of design
parameters.