13-06-2012, 12:19 PM
Design of On-Chip Bus with OCP Interface
[attachment=24285]
Abstract
As more and more IP cores are integrated into
an SOC design, the communication flow between IP cores
has increased drastically and the efficiency of the on-chip
bus has become a dominant factor for the performance of
a system. The on-chip bus design can be divided into two
parts, namely the interface and the internal architecture of
the bus. In this work we adopt the well-defined interface
standard, the Open Core Protocol (OCP), and focus on the
design of the internal bus architecture.
INTRODUCTION
An SOC chip usually contains a large number of IP cores
that communicate with each other through on-chip buses. As
the VLSI process technology continuously advances, the
frequency and the amount of the data communication between
IP cores increase substantially. As a result, the ability of onchip
buses to deal with the large amount of data traffic
becomes a dominant factor for the overall performance.
ON-CHIP BUS FUNCTIONALITIES
We first describe the various bus functionalities including
1) burst, 2) lock, 3) pipelined, and 4) out-of-order transactions.
Burst transactions
The burst transactions allow the grouping of multiple
transactions that have a certain address relationship, and can
be classified into multi-request burst and single-request burst
according to how many times the addresses are issued.
FIGURE 1 shows the two types of burst read transactions. The
multi-request burst as defined in AHB is illustrated in
FIGURE 1(a) where the address information must be issued
for each command of a burst transaction.
CONCLUSIONS
The current trend of the bus standard is to define an
explicit bus interface and leave the internal bus architecture to
the bus designer. The design which complies with the bus
interface protocol to carry out the various advanced bus
functionality consequently dominates the communication
efficiency of an SOC system. In this work, we develop an onchip
bus employing OCP as the bus interface. Various bus
transactions defined in AXI and OCP to reduce the
communication latency and increase the bus throughput are
supported by the proposed bus architecture. Experimental
results demonstrate the efficiency of the proposed bus in both
simulation speed and execution performance.
[attachment=24285]
Abstract
As more and more IP cores are integrated into
an SOC design, the communication flow between IP cores
has increased drastically and the efficiency of the on-chip
bus has become a dominant factor for the performance of
a system. The on-chip bus design can be divided into two
parts, namely the interface and the internal architecture of
the bus. In this work we adopt the well-defined interface
standard, the Open Core Protocol (OCP), and focus on the
design of the internal bus architecture.
INTRODUCTION
An SOC chip usually contains a large number of IP cores
that communicate with each other through on-chip buses. As
the VLSI process technology continuously advances, the
frequency and the amount of the data communication between
IP cores increase substantially. As a result, the ability of onchip
buses to deal with the large amount of data traffic
becomes a dominant factor for the overall performance.
ON-CHIP BUS FUNCTIONALITIES
We first describe the various bus functionalities including
1) burst, 2) lock, 3) pipelined, and 4) out-of-order transactions.
Burst transactions
The burst transactions allow the grouping of multiple
transactions that have a certain address relationship, and can
be classified into multi-request burst and single-request burst
according to how many times the addresses are issued.
FIGURE 1 shows the two types of burst read transactions. The
multi-request burst as defined in AHB is illustrated in
FIGURE 1(a) where the address information must be issued
for each command of a burst transaction.
CONCLUSIONS
The current trend of the bus standard is to define an
explicit bus interface and leave the internal bus architecture to
the bus designer. The design which complies with the bus
interface protocol to carry out the various advanced bus
functionality consequently dominates the communication
efficiency of an SOC system. In this work, we develop an onchip
bus employing OCP as the bus interface. Various bus
transactions defined in AXI and OCP to reduce the
communication latency and increase the bus throughput are
supported by the proposed bus architecture. Experimental
results demonstrate the efficiency of the proposed bus in both
simulation speed and execution performance.