19-06-2012, 01:13 PM
Fermi-FET transistor technology
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INTRODUCTION
Transistor scaling, a major driving force in the industry for decades, has been responsible for the dramatic increase in circuit complexity. Shorter gate lengths have required lower drain voltages and concurrently lower threshold voltages. Recent CMOS evolution has seen a dramatic reduction in operating voltage as transistor size is reduced. This was due to the maximum field limit on the gate oxide needed to maintain good long-term reliability. Proper selection of the gate material can produce low threshold transistors with off-state performance parameters equivalent to high threshold devices.
The Buried Channel Accumulation device, currently being used for p-type transistor processes has the Fermi level at a considerable depth from the gate thereby making it difficult to shut the device off. Attempts to bring the Fermi level up result in severe degradation of device performance. Need for optimization of existing BCA technology arose and Thunderbird Technologies, Inc. delivered! The ‘incredible’: Fermi-FET.
The Fermi-FET technology brings the Fermi level nearer to the gate. This technology merges the mobility and low drain current leakage of BCA devices as well as the higher short channel effect immunity of SCI devices. This paper highlights aspects of the technology in a non-mathematical presentation to give a sound general understanding of why the technology is the most promising avenue for advanced very short devices.
Fermi-FET technology can lead to significant improvement in circuit performance, layout density, power requirements, and manufacturing cost with only a moderate alteration of traditional MOSFET manufacturing technology. This technology makes use of a subtle optimization of traditional buried channel technology to overcome the known shortcomings of buried channel while maintaining large improvements in channel mobility.
Fermi-FET can optimize both the N-Channel and P-Channel devices with a single gate material, provided the work function is near the mid-range between N and P-type polysilicon. Materials that have been used in MOSFET technology with a suitable work function include Tungsten, Tungsten Silicide, Nickel, Cobalt, Cobalt Silicide, P-type Ge: Si and many others. There is about a 30% reduction in junction capacitance relative to traditional MOSFET devices. This fact alone gives a significant speed advantage to the Fermi-FET in large scale circuits. The total speed improvement produced by both the lowered threshold and lowered gate and junction capacitances is very substantial.
In order to illustrate the impact of lowered threshold voltages via work function engineering, the large-signal transient response of two inverter structures was simulated. A comparison of conventional CMOS and metal-gate Fermi-FET structures was performed. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET. The different delay characteristics are evident. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET.
THE TRANSISTOR STRUCTURE
The Fermi-FET is a unique patented variation of the broad class of devices known as “Field Effect Transistors” (FET). Although the transistor operation differs markedly from standard MOSFET devices, the structure of the new device has many similarities, thus permitting easy conversion of existing CMOS process lines to production of Fermi-FET transistors.
BASIC FET
The basic principle behind the working of a Field Effect Transistor is the conducting semi-conductor channel between two ohmic contacts; source and drain. The gate terminal controls the channel current and is a very high-impedance terminal. The FET is thus a three terminal, unipolar device. The name ‘field effect’ is due to the fact that the current flow is controlled by potential set up in the device by an external applied voltage. There are two types of FETs – JFET and MOSFET. The FET of interest here is the MOSFET.
The N-channel MOSFET has two lightly heavily doped n- regions diffused into a lightly doped p-type substrate; separated by 25μm.These n-regions act as source and drain. An insulating layer is grown over the surface. Metal contacts are made for the source and drain. A conducting layer of metal will act as the gate, overlaying the insulating layer over the entire channel region. Due to the presence of the insulating layer, the device is called Insulated Gate FET (IGFET) or Metal Oxide Semiconductor FET (MOSFET).
Modern Complementary MOS (CMOS) processes incorporate polysilicon gate structures less than 0.25 micron long, with the most common process being 0.15µm. At this geometry, and the standard 1.8 volt Vdd, oxide spacers and drain extensions are common. Most processes also make use of the oxide spacer to form salicide on the gate and diffusions to reduce the sheet resistance and to control the polytime constant on wide transistors.
SURFACE CHANNEL INVERSION DEVICES
Most short channel CMOS processes create SCI type transistors for both P and N-Channel devices. This decision has evolved as line widths attained shorter dimensions primarily due to the reduced short channel effect sensitivity of the SCI devices over the BCA transistor, traditionally used for the PMOS. Its because of the widely known control problems with deep buried channel transistor (BCA) technology that most short channel processes incorporate both n-type and p-type polysilicon gates to create surface channel inversion (SCI) devices for both transistor polarities.
[attachment=24783]
INTRODUCTION
Transistor scaling, a major driving force in the industry for decades, has been responsible for the dramatic increase in circuit complexity. Shorter gate lengths have required lower drain voltages and concurrently lower threshold voltages. Recent CMOS evolution has seen a dramatic reduction in operating voltage as transistor size is reduced. This was due to the maximum field limit on the gate oxide needed to maintain good long-term reliability. Proper selection of the gate material can produce low threshold transistors with off-state performance parameters equivalent to high threshold devices.
The Buried Channel Accumulation device, currently being used for p-type transistor processes has the Fermi level at a considerable depth from the gate thereby making it difficult to shut the device off. Attempts to bring the Fermi level up result in severe degradation of device performance. Need for optimization of existing BCA technology arose and Thunderbird Technologies, Inc. delivered! The ‘incredible’: Fermi-FET.
The Fermi-FET technology brings the Fermi level nearer to the gate. This technology merges the mobility and low drain current leakage of BCA devices as well as the higher short channel effect immunity of SCI devices. This paper highlights aspects of the technology in a non-mathematical presentation to give a sound general understanding of why the technology is the most promising avenue for advanced very short devices.
Fermi-FET technology can lead to significant improvement in circuit performance, layout density, power requirements, and manufacturing cost with only a moderate alteration of traditional MOSFET manufacturing technology. This technology makes use of a subtle optimization of traditional buried channel technology to overcome the known shortcomings of buried channel while maintaining large improvements in channel mobility.
Fermi-FET can optimize both the N-Channel and P-Channel devices with a single gate material, provided the work function is near the mid-range between N and P-type polysilicon. Materials that have been used in MOSFET technology with a suitable work function include Tungsten, Tungsten Silicide, Nickel, Cobalt, Cobalt Silicide, P-type Ge: Si and many others. There is about a 30% reduction in junction capacitance relative to traditional MOSFET devices. This fact alone gives a significant speed advantage to the Fermi-FET in large scale circuits. The total speed improvement produced by both the lowered threshold and lowered gate and junction capacitances is very substantial.
In order to illustrate the impact of lowered threshold voltages via work function engineering, the large-signal transient response of two inverter structures was simulated. A comparison of conventional CMOS and metal-gate Fermi-FET structures was performed. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET. The different delay characteristics are evident. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET.
THE TRANSISTOR STRUCTURE
The Fermi-FET is a unique patented variation of the broad class of devices known as “Field Effect Transistors” (FET). Although the transistor operation differs markedly from standard MOSFET devices, the structure of the new device has many similarities, thus permitting easy conversion of existing CMOS process lines to production of Fermi-FET transistors.
BASIC FET
The basic principle behind the working of a Field Effect Transistor is the conducting semi-conductor channel between two ohmic contacts; source and drain. The gate terminal controls the channel current and is a very high-impedance terminal. The FET is thus a three terminal, unipolar device. The name ‘field effect’ is due to the fact that the current flow is controlled by potential set up in the device by an external applied voltage. There are two types of FETs – JFET and MOSFET. The FET of interest here is the MOSFET.
The N-channel MOSFET has two lightly heavily doped n- regions diffused into a lightly doped p-type substrate; separated by 25μm.These n-regions act as source and drain. An insulating layer is grown over the surface. Metal contacts are made for the source and drain. A conducting layer of metal will act as the gate, overlaying the insulating layer over the entire channel region. Due to the presence of the insulating layer, the device is called Insulated Gate FET (IGFET) or Metal Oxide Semiconductor FET (MOSFET).
Modern Complementary MOS (CMOS) processes incorporate polysilicon gate structures less than 0.25 micron long, with the most common process being 0.15µm. At this geometry, and the standard 1.8 volt Vdd, oxide spacers and drain extensions are common. Most processes also make use of the oxide spacer to form salicide on the gate and diffusions to reduce the sheet resistance and to control the polytime constant on wide transistors.
SURFACE CHANNEL INVERSION DEVICES
Most short channel CMOS processes create SCI type transistors for both P and N-Channel devices. This decision has evolved as line widths attained shorter dimensions primarily due to the reduced short channel effect sensitivity of the SCI devices over the BCA transistor, traditionally used for the PMOS. Its because of the widely known control problems with deep buried channel transistor (BCA) technology that most short channel processes incorporate both n-type and p-type polysilicon gates to create surface channel inversion (SCI) devices for both transistor polarities.