19-06-2012, 03:46 PM
A VLSI PROGRESSIVE CODING FOR WAVELET-BASED IMAGE COMPRESSION
[attachment=24821]
Introduction
A majority of today’s Internet bandwidth is estimated to be used for images and video. Wavelet based techniques such as JPEG2000 for image compression has a lot more to offer than conventional methods in terms of compression ratio. The main aim of the project is to implement and verify the image compression technique and to investigate the possibility of hardware acceleration of DWT for signal processing applications. A hardware design has to be provided to achieve high performance, in comparison to the software implementation of DWT. EDK Tool (XPS 8.1i), Matlab 7, Visual Basic 6.0, Xilinx Spartan-3E FPGA Kit
Languages Used: System C., JPEG2000 (SPHIT), FDWT
Conclusion
The architecture has been implemented using .c The model has been verified with a set of text data. the derived architecture has many advantages especially the reduction in the number of operations per sample, leading to a reduced chip area and power consumption .it can be said that the original design criteria has been considered and an effective and feasible architecture has been designed.
The major disadvantage of this design is that it cannot perform online transform i.e. the output will not be generated in all instance of data input, this work can be further extended by using multi processor architecture to speed up the data usage. The maximum clock speed achievable is around 131.6 MHz
[attachment=24821]
Introduction
A majority of today’s Internet bandwidth is estimated to be used for images and video. Wavelet based techniques such as JPEG2000 for image compression has a lot more to offer than conventional methods in terms of compression ratio. The main aim of the project is to implement and verify the image compression technique and to investigate the possibility of hardware acceleration of DWT for signal processing applications. A hardware design has to be provided to achieve high performance, in comparison to the software implementation of DWT. EDK Tool (XPS 8.1i), Matlab 7, Visual Basic 6.0, Xilinx Spartan-3E FPGA Kit
Languages Used: System C., JPEG2000 (SPHIT), FDWT
Conclusion
The architecture has been implemented using .c The model has been verified with a set of text data. the derived architecture has many advantages especially the reduction in the number of operations per sample, leading to a reduced chip area and power consumption .it can be said that the original design criteria has been considered and an effective and feasible architecture has been designed.
The major disadvantage of this design is that it cannot perform online transform i.e. the output will not be generated in all instance of data input, this work can be further extended by using multi processor architecture to speed up the data usage. The maximum clock speed achievable is around 131.6 MHz