23-06-2012, 11:17 AM
FPGA based FFT Algorithm Implementation in WiMAX Communications System
[attachment=25184]
INTRODUCTION
WiMAX – which stands for Worldwide Interoperability for
Microwave Access is bringing the wireless and Internet
revolutions to portable devices across the globe. Just as
broadcast television in the 1940’s and 1950’s changed the
world of entertainment, advertising, and our social fabric,
WiMAX is poised to broadcast the Internet throughout the
world, and the changes in our lives will be dramatic. WiMAX
is providing the capabilities of the Internet, without any wires,
to every living room, portable computer, phone, and handheld
device. The WiMAX modules utilize the OFDMA scheme in
their physical layer of communication.
IMPLEMENTATION IN VERILOG
VERILOG Hardware Description Language (VERILOG)
was introduced by Gateway Design Automation in 1984 as a
proprietary hardware description and simulation language [8,
9]. VERILOG synthesis tools can create logic-circuit structures
directly from VERILOG behavioral descriptions, and target
them to a selected technology for realization. Using
VERILOG, we can design, simulate, and synthesize anything
form a simple combinational circuit to a complete
microprocessor system on a chip. VERILOG started out as
documentation and modeling language, allowing the behavior
of digital-system designs to be precisely specified and
simulated [8, 9] and language specification allows multiple
modules to be stored in a single text file.
IMPLEMENTATION OF THE PROPOSED FFT IN OFDM COMMUNICATION SYSTEM
The fundamental principle of the OFDM system is to
decompose the high rate data stream (bandwidth=W) into N
lower rate data streams and then to transmit them
simultaneously over a large number of subcarriers [14]. The
IFFT and the FFT are used for, respectively, modulating and
demodulating the data constellations on the orthogonal
subcarriers [12].
In an OFDM system, the transmitter and receiver blocks
contain the FFT modules as shown in Fig. 4 (a) and (b). The
FFT processor must finish the transform within 312.5 ns to
serve the purpose in the OFDM system. Our FFT architecture
effectively fits into the system since it has a minimum
required time period of 10.827 ns (Table 1 (b)).
IMPLEMENTATION OF THE PROPOSED FFT IN FIXED& MOBILEWIMAX STANDARDS
The radix-4 butterfly needs 3 complex adders and 1
complex multiplier [16, 17], while the proposed butterfly
structure needs only 4 complex adders and 1 complex
multiplier. This is because our design implements the constant
multiplier by 4 reused complex adders. All of the abovementioned
use separated single Static Random Access
Memory (SRAM) into 2 smaller SRAMs. This design can
double SRAM throughput with inter-leaving access. In Table 2,
the hardware requirement of the proposed design is compared
with various pipelined designs.
CONCLUSIONS
We have proposed a memory based recursive FFT design
which has much less gate counts, lower power consumption
and higher speed. The proposed architecture has three main
advantages (1) fewer butterfly iteration to reduce power
consumption, (2) pipeline of radix-22 butterfly to speed up
clock frequency, (3) even distribution of memory access to
make utilization efficiency in SRAM ports. In summary, the
speed performance of our design easily satisfies most
application requirements of Fixed 802.16d and Mobile
802.16e WiMAX, which uses OFDMA modulated wireless
communication system. Our design also occupies lesser area,
hence lower cost and power consumption.
[attachment=25184]
INTRODUCTION
WiMAX – which stands for Worldwide Interoperability for
Microwave Access is bringing the wireless and Internet
revolutions to portable devices across the globe. Just as
broadcast television in the 1940’s and 1950’s changed the
world of entertainment, advertising, and our social fabric,
WiMAX is poised to broadcast the Internet throughout the
world, and the changes in our lives will be dramatic. WiMAX
is providing the capabilities of the Internet, without any wires,
to every living room, portable computer, phone, and handheld
device. The WiMAX modules utilize the OFDMA scheme in
their physical layer of communication.
IMPLEMENTATION IN VERILOG
VERILOG Hardware Description Language (VERILOG)
was introduced by Gateway Design Automation in 1984 as a
proprietary hardware description and simulation language [8,
9]. VERILOG synthesis tools can create logic-circuit structures
directly from VERILOG behavioral descriptions, and target
them to a selected technology for realization. Using
VERILOG, we can design, simulate, and synthesize anything
form a simple combinational circuit to a complete
microprocessor system on a chip. VERILOG started out as
documentation and modeling language, allowing the behavior
of digital-system designs to be precisely specified and
simulated [8, 9] and language specification allows multiple
modules to be stored in a single text file.
IMPLEMENTATION OF THE PROPOSED FFT IN OFDM COMMUNICATION SYSTEM
The fundamental principle of the OFDM system is to
decompose the high rate data stream (bandwidth=W) into N
lower rate data streams and then to transmit them
simultaneously over a large number of subcarriers [14]. The
IFFT and the FFT are used for, respectively, modulating and
demodulating the data constellations on the orthogonal
subcarriers [12].
In an OFDM system, the transmitter and receiver blocks
contain the FFT modules as shown in Fig. 4 (a) and (b). The
FFT processor must finish the transform within 312.5 ns to
serve the purpose in the OFDM system. Our FFT architecture
effectively fits into the system since it has a minimum
required time period of 10.827 ns (Table 1 (b)).
IMPLEMENTATION OF THE PROPOSED FFT IN FIXED& MOBILEWIMAX STANDARDS
The radix-4 butterfly needs 3 complex adders and 1
complex multiplier [16, 17], while the proposed butterfly
structure needs only 4 complex adders and 1 complex
multiplier. This is because our design implements the constant
multiplier by 4 reused complex adders. All of the abovementioned
use separated single Static Random Access
Memory (SRAM) into 2 smaller SRAMs. This design can
double SRAM throughput with inter-leaving access. In Table 2,
the hardware requirement of the proposed design is compared
with various pipelined designs.
CONCLUSIONS
We have proposed a memory based recursive FFT design
which has much less gate counts, lower power consumption
and higher speed. The proposed architecture has three main
advantages (1) fewer butterfly iteration to reduce power
consumption, (2) pipeline of radix-22 butterfly to speed up
clock frequency, (3) even distribution of memory access to
make utilization efficiency in SRAM ports. In summary, the
speed performance of our design easily satisfies most
application requirements of Fixed 802.16d and Mobile
802.16e WiMAX, which uses OFDMA modulated wireless
communication system. Our design also occupies lesser area,
hence lower cost and power consumption.