23-06-2012, 12:57 PM
SICAN Microelectronics
[attachment=25227]
General Description
The SICAN CAN core provides all CAN specification 2.0B
protocol functions including Extended CAN (2.0B active)
functionality. The core can support acceptance filtering
(implemented in external user logic) according to Basic
CAN (mask and code registers are similar to the Philips
82C200) or according to Full CAN (similar to the Intel
82527). It is also possible to combine the two processes.
The core incorporates all features required from the CAN
specification including error handling capabilities, stuff bit
generation, CRC, and multiple sample points. It has a universal
interface to connect to the receive and transmit buffers,
allowing the module to be optimized for specific
applications.
Functional Description
The CAN core is divided into modules as shown in the
block diagram of Figure 2. The core module has no receive
buffer memory. Basic operation is described below.
Rx and Tx – CAN Bus Interface
The CAN core uses a simple two-wire (Rx and Tx) connection.
Both signals operate at TTL levels that comply with
ISO/DIS 11898 so it can connect to standard CAN bus
transceivers (e.g. Philips PCA 82C250, Bosch CF150 or
Siliconix SI 9200) or to a modified RS-485 interface.
Receive and Transmit Error Counters
The CAN protocol contains mechanisms for automatic fault
location and for switching-off defective nodes. This is implemented
through two counters - a Receive Error Counter
(REC) and a Transmit Error Counter (TEC). These are
incremented and decremented according to CAN specification
rules.
Pinout
The pinout is not fixed to any specific device I/O. By itself,
the CAN core has 71 I/O. Signal names are provided in the
block diagram shown in Figure 1, and described in Table 1.
When using the optional User Module, with a 16-bit wide
DATA bus the I/O count for the combined design is 43. All I/
Os of the CAN User Module connect to a microcontroller
and external CAN transceivers. The User Module is like a
shell around the CAN core module. None of the core I/O
signals can be accessed from outside. Every access to the
core is made via the User Module. Signals for this configuration
are described in Table 2.
[attachment=25227]
General Description
The SICAN CAN core provides all CAN specification 2.0B
protocol functions including Extended CAN (2.0B active)
functionality. The core can support acceptance filtering
(implemented in external user logic) according to Basic
CAN (mask and code registers are similar to the Philips
82C200) or according to Full CAN (similar to the Intel
82527). It is also possible to combine the two processes.
The core incorporates all features required from the CAN
specification including error handling capabilities, stuff bit
generation, CRC, and multiple sample points. It has a universal
interface to connect to the receive and transmit buffers,
allowing the module to be optimized for specific
applications.
Functional Description
The CAN core is divided into modules as shown in the
block diagram of Figure 2. The core module has no receive
buffer memory. Basic operation is described below.
Rx and Tx – CAN Bus Interface
The CAN core uses a simple two-wire (Rx and Tx) connection.
Both signals operate at TTL levels that comply with
ISO/DIS 11898 so it can connect to standard CAN bus
transceivers (e.g. Philips PCA 82C250, Bosch CF150 or
Siliconix SI 9200) or to a modified RS-485 interface.
Receive and Transmit Error Counters
The CAN protocol contains mechanisms for automatic fault
location and for switching-off defective nodes. This is implemented
through two counters - a Receive Error Counter
(REC) and a Transmit Error Counter (TEC). These are
incremented and decremented according to CAN specification
rules.
Pinout
The pinout is not fixed to any specific device I/O. By itself,
the CAN core has 71 I/O. Signal names are provided in the
block diagram shown in Figure 1, and described in Table 1.
When using the optional User Module, with a 16-bit wide
DATA bus the I/O count for the combined design is 43. All I/
Os of the CAN User Module connect to a microcontroller
and external CAN transceivers. The User Module is like a
shell around the CAN core module. None of the core I/O
signals can be accessed from outside. Every access to the
core is made via the User Module. Signals for this configuration
are described in Table 2.