25-06-2012, 04:53 PM
Technical Seminar On Embedded DRAM
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INTRODUCTION
Even though the word DRAM has been quite common among us for many decades, the development in the field of DRAM was very slow.
The storage medium reached the present state of semiconductor after a long scientific research.
Once the semiconductor storage medium was well accepted by all, plans were put forward to integrate the logic circuits associated with the DRAM along with the DRAM itself.
However, technological complexities and economic justification for such a complex integrated circuit are difficult hurdles to overcome.
Although scientific breakthroughs are numerous in the commodity DRAM industry, similar techniques are not always appropriate when high- performance logic circuits are included on the same substrate.
Hence, Embedded DRAM pioneers have begun to develop numerous integration schemes.
WHY Embedded DRAM?
As application-specific integrated circuit (ASIC) technologies expand into new markets, the need for denser embedded memory grows. To accommodate this increase demand, embedded DRAM macros have been offered in state-of-the-art ASIC library portfolios. * It can be made clear from this report that embedded DRAM macro extends the on-chip capacity largely, allowing historically off-chip memory to be integrated on chip and enabling System-on-a-Chip (SoC) designs.
Fundamental DRAM operation
Embedded DRAM working can be explained effectively starting with DRAM working.
DRAM memory arrays are composed of word lines (or rows) and bit lines (columns);
At the cross point of every row and column is a storage cell consisting of a transistor and capacitor.
The data state of the cell is stored as charge on the capacitor, with the transistor acting as a switch controlling access to the capacitor. With the switch on (word line activated), charge can be read from or written to the storage cell.
The rest of the DRAM support circuits are dedicated to controlling the word lines and bit lines to -read and write the memory array.
DRAM-based Embedded DRAM
DRAM-based embedded DRAM chips begin with DRAM process architecture, usually one with two metal layers, on top of which one extra metal layer is added for logic routing.
The philosophy behind this type of embedded DRAM is usually the same as that employed by discrete commodity DRAM manufacturers.
This is to make the cell as small as possible, since a smaller cell means a smaller die, and thus a less expensive one.
CONCLUSION
After more than 30 years of process development, the DRAM storage medium can now be integrated on the same substrate containing meaningful amounts of high- performance Boolean logic. Embedded DRAM technology offerings will support memory sizes up to 64 Mb with little constraint associated with its minimum size or modularity and high-performance logic functions .
[attachment=25481]
INTRODUCTION
Even though the word DRAM has been quite common among us for many decades, the development in the field of DRAM was very slow.
The storage medium reached the present state of semiconductor after a long scientific research.
Once the semiconductor storage medium was well accepted by all, plans were put forward to integrate the logic circuits associated with the DRAM along with the DRAM itself.
However, technological complexities and economic justification for such a complex integrated circuit are difficult hurdles to overcome.
Although scientific breakthroughs are numerous in the commodity DRAM industry, similar techniques are not always appropriate when high- performance logic circuits are included on the same substrate.
Hence, Embedded DRAM pioneers have begun to develop numerous integration schemes.
WHY Embedded DRAM?
As application-specific integrated circuit (ASIC) technologies expand into new markets, the need for denser embedded memory grows. To accommodate this increase demand, embedded DRAM macros have been offered in state-of-the-art ASIC library portfolios. * It can be made clear from this report that embedded DRAM macro extends the on-chip capacity largely, allowing historically off-chip memory to be integrated on chip and enabling System-on-a-Chip (SoC) designs.
Fundamental DRAM operation
Embedded DRAM working can be explained effectively starting with DRAM working.
DRAM memory arrays are composed of word lines (or rows) and bit lines (columns);
At the cross point of every row and column is a storage cell consisting of a transistor and capacitor.
The data state of the cell is stored as charge on the capacitor, with the transistor acting as a switch controlling access to the capacitor. With the switch on (word line activated), charge can be read from or written to the storage cell.
The rest of the DRAM support circuits are dedicated to controlling the word lines and bit lines to -read and write the memory array.
DRAM-based Embedded DRAM
DRAM-based embedded DRAM chips begin with DRAM process architecture, usually one with two metal layers, on top of which one extra metal layer is added for logic routing.
The philosophy behind this type of embedded DRAM is usually the same as that employed by discrete commodity DRAM manufacturers.
This is to make the cell as small as possible, since a smaller cell means a smaller die, and thus a less expensive one.
CONCLUSION
After more than 30 years of process development, the DRAM storage medium can now be integrated on the same substrate containing meaningful amounts of high- performance Boolean logic. Embedded DRAM technology offerings will support memory sizes up to 64 Mb with little constraint associated with its minimum size or modularity and high-performance logic functions .