26-06-2012, 03:35 PM
Energy-efficiency for Modern Electronic Systems
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Abstract
We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18- m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply.
INTRODUCTION
Energy-efficiency is one of the most required features for modern electronic systems designed for high-performance and/or portable applications. In one hand, the ever increasing market segment of portable electronic devices demands the availability of low-power building blocks that enable the implementation of long-lasting battery-operated systems. On the other hand, the general trend of increasing operating frequencies and circuit complexity, in order to cope with the throughput needed in modern high-performance processing applications, requires the design of very high-speed circuits. The power-delay product (PDP) metric relates the amount of energy spent during the realization of a determined task, and stands as the more fair performance metricwhen comparing optimizations of a module designed and tested using different technologies, operating frequencies, and scenarios.
PREVIOUS FULL-ADDER OPTIMIZATIONS
Many papers have been published regarding the optimization of low-power full-adders, trying different options for the logic style (standard CMOS [2], differential cascade voltage switch (DCVS) [3], complementary pass-transistor logic (CPL) [4], double pass-transistor logic (DPL) [5], swing restored CPL (SR-CPL) [6], and hybrid styles [7]–[9]), and the logic structure used to build the adder module [10],[ 11]. The internal logic structure shown in Fig. 1 [12] has been adopted as the standard configuration in most of the enhancements developed for the 1-bit full-adder module. In this configuration, the adder module is formed by three main logical blocks.
[attachment=25612]
Abstract
We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18- m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply.
INTRODUCTION
Energy-efficiency is one of the most required features for modern electronic systems designed for high-performance and/or portable applications. In one hand, the ever increasing market segment of portable electronic devices demands the availability of low-power building blocks that enable the implementation of long-lasting battery-operated systems. On the other hand, the general trend of increasing operating frequencies and circuit complexity, in order to cope with the throughput needed in modern high-performance processing applications, requires the design of very high-speed circuits. The power-delay product (PDP) metric relates the amount of energy spent during the realization of a determined task, and stands as the more fair performance metricwhen comparing optimizations of a module designed and tested using different technologies, operating frequencies, and scenarios.
PREVIOUS FULL-ADDER OPTIMIZATIONS
Many papers have been published regarding the optimization of low-power full-adders, trying different options for the logic style (standard CMOS [2], differential cascade voltage switch (DCVS) [3], complementary pass-transistor logic (CPL) [4], double pass-transistor logic (DPL) [5], swing restored CPL (SR-CPL) [6], and hybrid styles [7]–[9]), and the logic structure used to build the adder module [10],[ 11]. The internal logic structure shown in Fig. 1 [12] has been adopted as the standard configuration in most of the enhancements developed for the 1-bit full-adder module. In this configuration, the adder module is formed by three main logical blocks.