28-06-2012, 01:13 PM
A FUZZY LOGIC APPROACH TO ENCRYPTED WATERMARKING FOR STILL IMAGES IN WAVELET DOMAIN ON FPGA
[attachment=25918]
Introduction
Digital right management is the collection of technologies and techniques that
enables the licensing of the digital information. This includes the multimedia property like
image, video, music etc.
The success in the digital revolution and internet introduces the new set of problems
regarding security. The digital content providers are unwilling to distribute their multimedia
content such as images over internet due to lack of security. Digital revolution provides tool
to unlimited copying without fidelity loss [1].
Digital watermarking is defined as a process of informed signal (watermark) into
multimedia content such as image to protect the owner’s right to that content. Later
watermark extracted from suspected image verified for the ownership identification [2].
For still digital images there are three primary methods for insertion and extraction of
watermark. These are spatial domain methods, transform domain and color space methods.
Spatial domain method [3] provides algorithm that directly operate on the pixel values of the
of the host image. In the transform domain the pixel values are transformed into another
domain by applying appropriate transform like DCT [4][5][6], DWT [7][8] etc. and then
embedded a watermark by modifying these coefficients. But it is seen that the spatial domain
watermarks are weaker than the frequency domain.
DWT and IDWT Processor
The discrete wavelet transform is popular being a very effective signal analysis tool
for many practical applications like image watermarking. DWT can analyze the data in
different scales and resolutions this principal is called as multi-resolution analysis [11].
Its characteristics well suited for image watermarking which includes the ability to
take into account of Human Visual System’s (HVS) characteristics. It is also a basis of a
compression standards like JPEG2000 [13] and MPEG-4[12].
Watermark Generation
Watermark generation unit generates the necessary encryption watermarking bit. This
block has two input key C and the watermarking bit. Block generates the PN sequence by
using LFSR (Linear Feedback Shift Register) with known key C. The generated PN sequence
and watermark bit is XOR sequentially to generate the encrypted bit
Watermarking Insertion Unit
The figure 4 shows the watermark insertion unit. This unit calculates the NN of the
LL band in a given block and inset the watermark by modifying the NN. Two adders and two
right shift operations are used to calculate the NN. To modify the NN of the block the
calculated NN and the I(i, j) is multiplied by scaling factor. These two quantities are added
together to get modified value of I (i,j). According to equation (6) if the watermark bit is to
select the modified value or not to change the value this operation is performed by 2:1
multiplexer.
Synthesis and Implementation
The chip was modeled using a Verilog HDL and the functional simulation was
performed. The code was synthesized on XC3SD1800A-4FGG676C device using AccelDSP
tool from Xilinx. The results are verified using the hardware co-simulation using AccelDSP.
The hardware co-simulation run at 33.3 MHz clock frequency and samples are fed to the
target device at the rate of 448.76KSPS through JTAG USB cable. The design utilizes the 204
startup clock cycles and 203 clock cycles for per function call.
[attachment=25918]
Introduction
Digital right management is the collection of technologies and techniques that
enables the licensing of the digital information. This includes the multimedia property like
image, video, music etc.
The success in the digital revolution and internet introduces the new set of problems
regarding security. The digital content providers are unwilling to distribute their multimedia
content such as images over internet due to lack of security. Digital revolution provides tool
to unlimited copying without fidelity loss [1].
Digital watermarking is defined as a process of informed signal (watermark) into
multimedia content such as image to protect the owner’s right to that content. Later
watermark extracted from suspected image verified for the ownership identification [2].
For still digital images there are three primary methods for insertion and extraction of
watermark. These are spatial domain methods, transform domain and color space methods.
Spatial domain method [3] provides algorithm that directly operate on the pixel values of the
of the host image. In the transform domain the pixel values are transformed into another
domain by applying appropriate transform like DCT [4][5][6], DWT [7][8] etc. and then
embedded a watermark by modifying these coefficients. But it is seen that the spatial domain
watermarks are weaker than the frequency domain.
DWT and IDWT Processor
The discrete wavelet transform is popular being a very effective signal analysis tool
for many practical applications like image watermarking. DWT can analyze the data in
different scales and resolutions this principal is called as multi-resolution analysis [11].
Its characteristics well suited for image watermarking which includes the ability to
take into account of Human Visual System’s (HVS) characteristics. It is also a basis of a
compression standards like JPEG2000 [13] and MPEG-4[12].
Watermark Generation
Watermark generation unit generates the necessary encryption watermarking bit. This
block has two input key C and the watermarking bit. Block generates the PN sequence by
using LFSR (Linear Feedback Shift Register) with known key C. The generated PN sequence
and watermark bit is XOR sequentially to generate the encrypted bit
Watermarking Insertion Unit
The figure 4 shows the watermark insertion unit. This unit calculates the NN of the
LL band in a given block and inset the watermark by modifying the NN. Two adders and two
right shift operations are used to calculate the NN. To modify the NN of the block the
calculated NN and the I(i, j) is multiplied by scaling factor. These two quantities are added
together to get modified value of I (i,j). According to equation (6) if the watermark bit is to
select the modified value or not to change the value this operation is performed by 2:1
multiplexer.
Synthesis and Implementation
The chip was modeled using a Verilog HDL and the functional simulation was
performed. The code was synthesized on XC3SD1800A-4FGG676C device using AccelDSP
tool from Xilinx. The results are verified using the hardware co-simulation using AccelDSP.
The hardware co-simulation run at 33.3 MHz clock frequency and samples are fed to the
target device at the rate of 448.76KSPS through JTAG USB cable. The design utilizes the 204
startup clock cycles and 203 clock cycles for per function call.