30-06-2012, 06:09 PM
Synthesizable IP-Core for configurable parallel CRC Architecture
[attachment=26390]
ABSTRACT
Cyclic redundancy check (CRC) is an error detecting code that is widely used to detect corruption in blocks of data that have been transmitted or stored. Hardware configurability that will allow unrestricted CRC sizes and polynomials to be deployed enables a wide range of network transmission, storage and security application.
In this research work, we derive a fully field programmable, parallel architecture for CRC computation circuit. The objective was to explore a domain specific programmable architecture capable of supporting 5Gb/s line rates at a minimal area cost. The resulting architecture is able to support all types and sizes of CRC polynomials, for all types of protocols and data encryption. The architecture has been designed to be field programmable so that it is fully flexible in terms of the polynomials deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. Data integrity is imperative for many network protocols, especially data-link layer protocols. Techniques using parity codes and hamming codes can be used for data verification, but CRC is preferred and most efficient method used for detecting bit errors produced from medium related noise.
The over all System Architecture will be designed using HDL language and simulation, synthesis and implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools. Finally the proposed system architecture performance (speed, area, power and throughput) will be compared with already exiting system implementations.
[attachment=26390]
ABSTRACT
Cyclic redundancy check (CRC) is an error detecting code that is widely used to detect corruption in blocks of data that have been transmitted or stored. Hardware configurability that will allow unrestricted CRC sizes and polynomials to be deployed enables a wide range of network transmission, storage and security application.
In this research work, we derive a fully field programmable, parallel architecture for CRC computation circuit. The objective was to explore a domain specific programmable architecture capable of supporting 5Gb/s line rates at a minimal area cost. The resulting architecture is able to support all types and sizes of CRC polynomials, for all types of protocols and data encryption. The architecture has been designed to be field programmable so that it is fully flexible in terms of the polynomials deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. Data integrity is imperative for many network protocols, especially data-link layer protocols. Techniques using parity codes and hamming codes can be used for data verification, but CRC is preferred and most efficient method used for detecting bit errors produced from medium related noise.
The over all System Architecture will be designed using HDL language and simulation, synthesis and implementation (Translation, Mapping, Placing and Routing) will be done using various FPGA based EDA Tools. Finally the proposed system architecture performance (speed, area, power and throughput) will be compared with already exiting system implementations.