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3D integration of nanophotonics with CMOS electronics

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INTRODUCTION

Silicon-on-Insulator (SOI) materials system has proven to be an efficient platform for the realization of both electronic and photonic devices. Recent years have seen significant amount of research in the area of silicon photonics, resulting in the demonstration of a variety of both active and passive optical functionalities. These technologies have demonstrated the feasibility of using silicon for the realization of integrated optical devices. One of the most attractive features of the silicon is the prospect of full integration of optical and electronic devices on the same substrate. On the other hand, the cost of manufacturing CMOS devices increases exponentially as the feature size continues to scale further down nano-scale dimensions, with the number of transistors projected to reach 2 billion per chip. In order for this scaling to be economically feasible, it becomes necessary to maximize the real estate usage on silicon wafers. It is desirable, therefore, to realize opto-electronic integration in silicon in such a way that the photonic devices consume minimal amount of real estate on a silicon wafer.


PROCESS OF SIMOX 3-D SCULPTING

SIMOX process involves the implantation of Oxygen ions into a Silicon substrate, followed by a high temperature anneal (around 1300ºC) of the substrate in order to cure the implantation damage and to effect SiO2 formation. The thickness and the depth of the buried oxide layer are respectively determined by the implantation dose and energy. It has been observed that in order to achieve good quality buried oxide and to keep the defect densities in the range of < 105 /cm2, implantation dose should be in the range of 1×1017-9×1017 ions per cm2, with implantation energies in the range of 40 – 200 KeV9. The process is conventionally used to obtain thin silicon layers (of the order of 3000 Ǻ) on top of a buried oxide layer of thickness of the same order of magnitude. There has been an attempt previously to fabricate 3-D structures in SOI wafers using the SIMOX process, combining it with epitaxial growth of Silicon10.


FABRICATION OF DEVICES

A SOI wafer (made by SOITEC Inc.) with 0.6 μm of Silicon on top of a buried oxide layer of 1.0 μm thickness was oxidized and patterned using reactive ion etching process to form oxide stripes of thickness 0.06 μm, and of width 2 μm. The patterned wafer was then implanted with oxygen ions with a dose of 5×1017 ions per cm2, at energy of 150 KeV. The implanted wafers were then annealed at 1320ºC for 7.5 hours in an ambient of Argon, with 1% Oxygen, to cure the implantation damage.


Subterranean Photonics

Figure 5 shows the transmission properties of the throughput port of the resonator, characterized using an Amplified Spontaneous Emission (ASE) source. The un-polarized light from the ASE source was passed through an inline fiber polarizer and a polarization controller that can rotate the state of polarization of the light to any desired state. This polarized light was coupled into the bus waveguides using a tapered fiber that has a spot diameter of 2 μm.