07-07-2012, 10:45 AM
A Fast Simulation Approach for Inductive Effects of VLSI Interconnects
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ABSTRACT:
Modeling on-chip inductive effects for interconnects of multiGHz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large number of mutual inductances. Meanwhile, ignoring the nonlinear behavior of drivers in a fast linear circuit simulator results in large errors for the inductive effect.
In this paper, a fast and accurate time-domain transient analysis approach is presented, which captures the non-linearity of circuit drivers, the effect of non-ideal ground and de-coupling capacitors in a bus structure. The proposed method models the non-linearity of drivers in conjunction with specific bus geometries.
INTRODUCTION
There is no doubt that our daily lives are significantly affected by electronic engineering technology. This is true on the domestic scene, in our professional disciplines, in the workplace, and in leisure activities.
The revolutionary changes have taken in this field in a relatively short time and it is also certain that even more dramatic advances will be made in the next decade.
WHAT IS INTERCONNECT
An interconnect in VLSI design consists of actual path between global routs and actual circuit. While interconnect the physical metal lines introduces R,L,C parameters that can have a dominant influence on the circuit operation, also this parasitic effects display a scaling behavior that is different from the active devices. Their effect increases as device dimensions are reduced and dominate the performance in submicron technologies.
SYSTEM OVERVIEW
There has been some previously reported work on improving the efficiency of simulating interconnects including inductance. The effective capacitance method for RC interconnect simulation has been extended to RLC interconnect simulation. The efficient Ceff model works in terms of pre-characterizing the parameters of a time varying Thevenin voltage source model (in series with a fixed resistor) over a wide range of effective capacitance load values.
SIMULATION EXAMPLES
Various examples from microprocessor designs are simulated with typical values to demonstrate the validity of the proposed scheme. Using 0.18 μm technology. Results from the new tool are compared with the ones from the full SPICE simulation which includes all the non-linear drivers.
CONCLUSIONS
Due to parallel routing and possible simultaneous switching of signals in a bus, mutual and self-inductance can cause additional delays and inductive noise for bus signals. A fast and accurate time-domain transient waveform simulation approach for RLC interconnect is presented. The capability to include the nonlinearity of drivers in a reduced-order linear circuit simulator enables a much faster yet accurate simulation of on-chip interconnects with inductance.
[attachment=27045]
ABSTRACT:
Modeling on-chip inductive effects for interconnects of multiGHz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large number of mutual inductances. Meanwhile, ignoring the nonlinear behavior of drivers in a fast linear circuit simulator results in large errors for the inductive effect.
In this paper, a fast and accurate time-domain transient analysis approach is presented, which captures the non-linearity of circuit drivers, the effect of non-ideal ground and de-coupling capacitors in a bus structure. The proposed method models the non-linearity of drivers in conjunction with specific bus geometries.
INTRODUCTION
There is no doubt that our daily lives are significantly affected by electronic engineering technology. This is true on the domestic scene, in our professional disciplines, in the workplace, and in leisure activities.
The revolutionary changes have taken in this field in a relatively short time and it is also certain that even more dramatic advances will be made in the next decade.
WHAT IS INTERCONNECT
An interconnect in VLSI design consists of actual path between global routs and actual circuit. While interconnect the physical metal lines introduces R,L,C parameters that can have a dominant influence on the circuit operation, also this parasitic effects display a scaling behavior that is different from the active devices. Their effect increases as device dimensions are reduced and dominate the performance in submicron technologies.
SYSTEM OVERVIEW
There has been some previously reported work on improving the efficiency of simulating interconnects including inductance. The effective capacitance method for RC interconnect simulation has been extended to RLC interconnect simulation. The efficient Ceff model works in terms of pre-characterizing the parameters of a time varying Thevenin voltage source model (in series with a fixed resistor) over a wide range of effective capacitance load values.
SIMULATION EXAMPLES
Various examples from microprocessor designs are simulated with typical values to demonstrate the validity of the proposed scheme. Using 0.18 μm technology. Results from the new tool are compared with the ones from the full SPICE simulation which includes all the non-linear drivers.
CONCLUSIONS
Due to parallel routing and possible simultaneous switching of signals in a bus, mutual and self-inductance can cause additional delays and inductive noise for bus signals. A fast and accurate time-domain transient waveform simulation approach for RLC interconnect is presented. The capability to include the nonlinearity of drivers in a reduced-order linear circuit simulator enables a much faster yet accurate simulation of on-chip interconnects with inductance.