07-07-2012, 12:50 PM
COMPARATOR
[attachment=27098]
Definition:
Compares the instantaneous values of two analog signals [() and ()] and
provides logical output to indicate their relative magnitudes (Logic ‘1’ for ;
Logic ‘0’ for ). Thus the comparator responds to analog inputs and provides a
digital output .
Schematic Representation:
Schematically, the input stage is a high gain differential amplifier (amplifies the
difference between the inputs, but rejects the common mode component), followed by a
decision making unit (latch), which ensures a sharp transition from one logic state to
another. The high gain of the analog amplifier stage may be achieved using one or more
stages. The latch is usually followed by a buffer stage to handle large capacitive loads.
Comparator Characteristics
The desired (ideal) and realistic (actual) input output characteristic of a comparator are
shown in Fig 3.
It is desirable that the output (of ideal Comparator) makes a sharp transition from Logic
‘0’ to Logic ‘1’, or vice versa, whenever the two input instantaneous values cross each
other. This implies infinite gain analog differential amplifier. However, typically a latch
is used as the decision making unit, which can achieve a sharp transition. The rise and
fall time is decided by the decision making stage.
Comparator Circuit Architecture
The input stage differential transcoductance amplifier is shown in Fig. 4. The gain of this
stage is rather low (because of the diode connected PMOS load M3-M4)); the low node
impedance ensures high speed (high bandwidth) operation. The fully differential output
ensures rejection of the common mode component of the input signal. The current
mirrors (M6-M7) acting on the fully differential output of the first stage, can be used to
impart a current gain ( by choosing a suitable W/L ratio). The diode connected NMOS
pair M8-M9, acts as low impedance load for this stage. The other NMOS pair (M10-
M11) with cross connected gates act as normal logic inverters forming a latch – the
decision circuit.
[attachment=27098]
Definition:
Compares the instantaneous values of two analog signals [() and ()] and
provides logical output to indicate their relative magnitudes (Logic ‘1’ for ;
Logic ‘0’ for ). Thus the comparator responds to analog inputs and provides a
digital output .
Schematic Representation:
Schematically, the input stage is a high gain differential amplifier (amplifies the
difference between the inputs, but rejects the common mode component), followed by a
decision making unit (latch), which ensures a sharp transition from one logic state to
another. The high gain of the analog amplifier stage may be achieved using one or more
stages. The latch is usually followed by a buffer stage to handle large capacitive loads.
Comparator Characteristics
The desired (ideal) and realistic (actual) input output characteristic of a comparator are
shown in Fig 3.
It is desirable that the output (of ideal Comparator) makes a sharp transition from Logic
‘0’ to Logic ‘1’, or vice versa, whenever the two input instantaneous values cross each
other. This implies infinite gain analog differential amplifier. However, typically a latch
is used as the decision making unit, which can achieve a sharp transition. The rise and
fall time is decided by the decision making stage.
Comparator Circuit Architecture
The input stage differential transcoductance amplifier is shown in Fig. 4. The gain of this
stage is rather low (because of the diode connected PMOS load M3-M4)); the low node
impedance ensures high speed (high bandwidth) operation. The fully differential output
ensures rejection of the common mode component of the input signal. The current
mirrors (M6-M7) acting on the fully differential output of the first stage, can be used to
impart a current gain ( by choosing a suitable W/L ratio). The diode connected NMOS
pair M8-M9, acts as low impedance load for this stage. The other NMOS pair (M10-
M11) with cross connected gates act as normal logic inverters forming a latch – the
decision circuit.