07-07-2012, 12:52 PM
Performance Evaluation of Bypassing Array Multiplier with Optimized Design
[attachment=27101]
INTRODUCTION
Multiplication is an essential arithmetic operation for common
DSP (Digital Signal Processors) and Microprocessor
applications. In recent years the researchers are emphasizes on
three areas i.e power, speed and area. Need of more applications
on a single processor will increase the number of transistors on a
chip and cause increases to power consumption. Hence among
the three fields one of the most important areas to be concentrate
is the power. To achieve high execution speed, parallel array
multipliers are widely used. These multipliers tend to consume
most of the power in DSP computations, and thus powerefficient
multipliers are very important for the design of lowpower
DSP systems [1], [2].
Array Multiplier
In the Carry Save Addition method, the first row can be
designed with either Half-Adders or Full-Adders. We have to
multiply two bits (one partial product) each from X and Y. If the
first row of the partial products is implemented with full adders,
then the third input i.e Cin will be considered ‗0‘. The carries of
each full adder can be diagonally forwarded to the next row of
the adder.
BYPASSING TECHNIQUE
Dynamic power consumption can be reduced by bypassing
method when the multiplier has more zeros in input data. To
perform isolation, transmission gates can be used, as ideal
switches with small power consumption, propagation delay
similar to the inverter and small area [7]. To study the proposed
design we have consider column bypassing multiplier in which
columns of adders are bypassed. In this multiplier, the
operations in a column can be disabled if the corresponding bit
in the multiplicand is 0. The advantage of this multiplier is it
eliminates the extra correcting circuit [8].
RESULTS AND DISCUSSIONS
The power, delay and energy delay product
comparison of full adders are given in the ―Table 1‖.The results
are carried out with the use of Tanner EDA tool and H-Spice.
Among the four types of full adders 16-T full adder shows good
efficiency in energy delay product. Though it shows good
efficiency due to less transistor count 14-T full adder (which
also has less power consumption little bit more than 16-T) is
used to design the multiplier.
The comparison of CSA and CSA without RCA in
power, delay and energy delay product is given in the ―Table 2‖.
Due to 56 less transistors CSA without RCA shows less power
consumption, delay efficient and also occupy less area. The
proposed method also applied to column bypassing multiplier
and the results are discussed below.
[attachment=27101]
INTRODUCTION
Multiplication is an essential arithmetic operation for common
DSP (Digital Signal Processors) and Microprocessor
applications. In recent years the researchers are emphasizes on
three areas i.e power, speed and area. Need of more applications
on a single processor will increase the number of transistors on a
chip and cause increases to power consumption. Hence among
the three fields one of the most important areas to be concentrate
is the power. To achieve high execution speed, parallel array
multipliers are widely used. These multipliers tend to consume
most of the power in DSP computations, and thus powerefficient
multipliers are very important for the design of lowpower
DSP systems [1], [2].
Array Multiplier
In the Carry Save Addition method, the first row can be
designed with either Half-Adders or Full-Adders. We have to
multiply two bits (one partial product) each from X and Y. If the
first row of the partial products is implemented with full adders,
then the third input i.e Cin will be considered ‗0‘. The carries of
each full adder can be diagonally forwarded to the next row of
the adder.
BYPASSING TECHNIQUE
Dynamic power consumption can be reduced by bypassing
method when the multiplier has more zeros in input data. To
perform isolation, transmission gates can be used, as ideal
switches with small power consumption, propagation delay
similar to the inverter and small area [7]. To study the proposed
design we have consider column bypassing multiplier in which
columns of adders are bypassed. In this multiplier, the
operations in a column can be disabled if the corresponding bit
in the multiplicand is 0. The advantage of this multiplier is it
eliminates the extra correcting circuit [8].
RESULTS AND DISCUSSIONS
The power, delay and energy delay product
comparison of full adders are given in the ―Table 1‖.The results
are carried out with the use of Tanner EDA tool and H-Spice.
Among the four types of full adders 16-T full adder shows good
efficiency in energy delay product. Though it shows good
efficiency due to less transistor count 14-T full adder (which
also has less power consumption little bit more than 16-T) is
used to design the multiplier.
The comparison of CSA and CSA without RCA in
power, delay and energy delay product is given in the ―Table 2‖.
Due to 56 less transistors CSA without RCA shows less power
consumption, delay efficient and also occupy less area. The
proposed method also applied to column bypassing multiplier
and the results are discussed below.